公开(公告)号：US5910927A

公开(公告)日：1999-06-08

申请号：US931525

申请日：1997-09-16

申请人： Takeshi Hamamoto ,  Masaki Tsukude

发明人： Takeshi Hamamoto ,  Masaki Tsukude

IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C7/065 ,  G11C8/10 ,  G11C8/14

摘要： A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).

摘要翻译： 提供具有较小电路面积但有效使用的存储器件。 沿着行方向延伸的多条主字线（MWL）通过相应的存储体锁存器（BL）连接到跨越银行（BANK0，BANK1）延伸的单个全局字线（GWL）。 使能信号（BLE）和全局字线（GWL）的选择性激活选择一个存储体锁存器（BL）来选择性地激活相关联的主字线（MWL）。 在使能信号（BLE）失效之后，该状态由选择的存储体锁存器（BL）保持。 然后，激活另一个使能信号（BLE）以选择性地激活另一主字线（MWL）。 连接到主字线（MWL）的子解码器（SD）彼此独立地选择，以独立地激活每个银行（BANK）的字线（WL）。

公开(公告)号：US5909046A

公开(公告)日：1999-06-01

申请号：US965618

申请日：1997-11-06

申请人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Tetsushi Tanizaki ,  Fukashi Morishita ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0248 ,  H01L24/05 ,  H01L2924/14

摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.

摘要翻译： 导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。 具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。 由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏 可以获得耐热性，并且可以获得耐喘振性的改善。

公开(公告)号：US5894448A

公开(公告)日：1999-04-13

申请号：US944642

申请日：1997-10-06

申请人： Teruhiko Amano ,  Masaki Tsukude

发明人： Teruhiko Amano ,  Masaki Tsukude

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C5/06 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/025

摘要： Memory mats provided in four regions formed by dividing a semiconductor chip are each further divided into a plurality of memory arrays along the longer side direction of the chip, row related circuits are provided between the memory arrays along the shorter side direction of the chip, and column decoders are provided along the longer side direction of the chip. An internal control signal from a master control circuit in the central part of the chip is transmitted in the central region with respect to the shorter side direction of the chip, buffer circuits are provided to an internal control signal transmission bus, and an internal signal is transmitted to the row related circuit and the column decoder by the buffer circuit. The length of the signal line to drive is shortened, and therefore the signal can be transmitted at a high speed, thus enabling high speed accessing. Thus, signal propagation delay can be reduced even if the chip size increases.

摘要翻译： 设置在通过划分半导体芯片形成的四个区域中的存储器垫每个被进一步沿着芯片的较长边方向分成多个存储器阵列，行相关电路沿着芯片的较短边方向设置在存储器阵列之间，并且 沿芯片的长边方向设置列解码器。 来自芯片中心的主控制电路的内部控制信号相对于芯片的短边方向在中央区域传输，缓冲电路被提供给内部控制信号传输总线，内部信号为 通过缓冲电路传输到行相关电路和列解码器。 要驱动的信号线的长度被缩短，因此可以高速传输信号，从而实现高速访问。 因此，即使芯片尺寸增加，也可以降低信号传播延迟。

公开(公告)号：US5408140A

公开(公告)日：1995-04-18

申请号：US139670

申请日：1993-10-22

申请人： Shinji Kawai ,  Masaki Tsukude ,  Yoshito Nakaoka

发明人： Shinji Kawai ,  Masaki Tsukude ,  Yoshito Nakaoka

IPC分类号： G11C11/413 ,  G05F3/20 ,  G11C5/14 ,  G11C11/408 ,  H03K19/094 ,  H03K3/01

CPC分类号： G11C5/146 ,  G05F3/205

摘要： A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p-channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.

摘要翻译： 衬底电位产生电路可以产生较低的衬底电位。 衬底电位产生电路包括时钟信号发生电路和第一和第二电荷泵电路。 包括其源电极连接到半导体衬底的p沟道MOS晶体管的第一电荷泵电路通过电容器的电容耦合向漏电极施加第一负电位。 包括第一和第二副电荷泵电路的第二电荷泵电路当第一负电位施加到漏电极时向栅电极施加第三负电位，然后通过降低第三电位而提供第二电位。 结果，p沟道MOS晶体管导通，直到衬底电位变成等于施加到漏电极的第一电位的电位，将衬底电位降低到第一电位。

公开(公告)号：US5022007A

公开(公告)日：1991-06-04

申请号：US506616

申请日：1990-04-10

申请人： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

发明人： Kazutami Arimoto ,  Yoshio Matsuda ,  Tsukasa Ooishi ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/34 ,  G11C29/56

CPC分类号： G11C29/56 ,  G11C29/34

摘要： A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.

摘要翻译： 一种用于半导体集成电路存储器的测试信号发生器，其中当传输晶体管（20,21,14,15）导通时，测试数据线从I / O线对（11,12）提供到 寄存器（10）并存储在其中。 当传送（67）导通时，写入寄存器的测试数据列以相同的模式写入存储单元（22）的列中，并且当传输晶体管（16,17）导通时，测试数据 写入寄存器的列被反相，并且写入存储单元列中，存储单元列中的数据被字线（13）读出并由读出放大器（5）放大，使得数据和测试 存储在寄存器中的数据由重合检测电路8进行比较，以检测其是否一致。

公开(公告)号：US07693004B2

公开(公告)日：2010-04-06

申请号：US12014071

申请日：2008-01-14

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.

摘要翻译： 本发明公开了一种具有产生驱动电源电压的电压供给电路的半导体存储器件。 电压供给电路设置有用于将驱动器电源电压预充电到存储单元的电源电压电平的第一电压供给电路和用于提供低于存储器的电源电压电平的电压的第二电压供应电路 电池作为驱动器电源电压。

公开(公告)号：US07447098B2

公开(公告)日：2008-11-04

申请号：US11976354

申请日：2007-10-24

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

摘要翻译： 在具有完全隐藏刷新功能的DRAM中，当在活动模式下执行数据刷新时，用于选择路径的信号被设置为“H”电平，然后在每个周期重置为“L”电平 指定相应的上位地址。 当在待机模式下进行数据更新时，选择路径的信号保持在“H”电平，并且在指定相应的上位地址时不会重置为“L”电平。 这可以减少待机电流。

公开(公告)号：US07301843B2

公开(公告)日：2007-11-27

申请号：US11375079

申请日：2006-03-15

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.

摘要翻译： 在具有完全隐藏刷新功能的DRAM中，当在活动模式下执行数据刷新时，用于选择路径的信号被设置为“H”电平，然后在每个周期重置为“L”电平 指定相应的上位地址。 当在待机模式下进行数据更新时，选择路径的信号保持在“H”电平，并且在指定相应的上位地址时不会重置为“L”电平。 这可以减少待机电流。

公开(公告)号：US06714047B2

公开(公告)日：2004-03-30

申请号：US10266757

申请日：2002-10-09

申请人： Tadayuki Shimizu ,  Masaki Tsukude ,  Takafumi Takatsuka

发明人： Tadayuki Shimizu ,  Masaki Tsukude ,  Takafumi Takatsuka

IPC分类号： H03K190185

CPC分类号： H03K19/018585 ,  H03K19/00384

摘要： The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.

摘要翻译： 半导体集成电路包括接收信号的输入电路，对接收信号施加预定功能的内部电路以及输出施加了预定功能的信号的输出电路。 将低于电压VDD的外部电源电压VDD和IO电源电压VDDQ提供给半导体集成电路。 通过降低外部电源电压VDD获得的电压VIO被提供给输入电路。 IO电源电压VDDQ被提供给输出电路。

公开(公告)号：US06628559B2

公开(公告)日：2003-09-30

申请号：US09971694

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Masaki Tsukude ,  Minoru Senda

发明人： Tadayuki Shimizu ,  Masaki Tsukude ,  Minoru Senda

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.