公开(公告)号：US08902640B2

公开(公告)日：2014-12-02

申请号：US13861681

申请日：2013-04-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L27/12 ,  H01L27/115 ,  G11C11/405 ,  H01L27/108 ,  G11C16/04

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US12183415B2

公开(公告)日：2024-12-31

申请号：US18203717

申请日：2023-05-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/4091 ,  H01L29/786 ,  H10B12/00

Abstract: A memory device that operates at high speed is provided.
The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

公开(公告)号：US12149237B2

公开(公告)日：2024-11-19

申请号：US18016888

申请日：2021-07-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki Ikeda ,  Shuhei Nagatsuka

IPC: H03K17/687 ,  G06F7/544 ,  H01L29/786 ,  G06G7/16

Abstract: A semiconductor device with high arithmetic performance is provided. The semiconductor device employs the translinear principle, and the semiconductor device includes first to tenth transistors each including a metal oxide in a channel formation region and a first capacitor. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor, a first terminal of the third transistor is electrically connected to a second terminal of the second transistor and a gate of the second transistor through the first capacitor. The second terminal of the second transistor is electrically connected to first terminals of the fourth and the seventh transistors and gates of the fifth and the eighth transistors. A gate of the seventh transistor is electrically connected to first terminals of the fifth and the sixth transistors, and a gate of the tenth transistor is electrically connected to first terminals of the eighth and the ninth transistors.

公开(公告)号：US11621443B2

公开(公告)日：2023-04-04

申请号：US17159214

申请日：2021-01-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Akihiro Kimura

IPC: H02J7/00 ,  H01M10/44 ,  H02J50/10 ,  H02J50/27 ,  H04B1/3883 ,  H02J50/40

Abstract: An electric power charge and discharge system for an electronic device having a battery, by which the electronic device can be used for a long period of time. In a wireless communication device including a wireless driving portion including a first battery and a wireless charging portion including a second battery, the first battery is charged by electric power from a fixed power supply and the second battery is charged by using electromagnetic waves existing in an external space. Further, the first battery and the second battery are discharged alternately, and during a period in which the first battery is discharged, the second battery is charged.

公开(公告)号：US11101300B2

公开(公告)日：2021-08-24

申请号：US16628920

申请日：2018-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki

IPC: H01L29/10 ,  H01L27/12

Abstract: A semiconductor device enabling high integration is provided. The semiconductor device includes a plug, two capacitors, and two transistors sharing one oxide semiconductor. Each of the transistors includes a stacked-layer structure of a gate insulator and a gate electrode over the oxide semiconductor and an insulator in contact with a side surface of the gate electrode. An opening between the two gate electrodes exposes the insulators in contact with the side surfaces of the gate electrodes, and the plug is in the opening. The capacitor is directly provided over the oxide semiconductor. The side surface area of the capacitor is larger than the projected area of the capacitor.

公开(公告)号：US10943646B2

公开(公告)日：2021-03-09

申请号：US16541239

申请日：2019-08-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4099 ,  H01L29/786 ,  G11C7/14 ,  G11C7/22 ,  G11C16/04 ,  G11C16/24 ,  G11C16/28 ,  H01L27/11529 ,  H01L27/1156 ,  G11C7/06

Abstract: A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

公开(公告)号：US10593683B2

公开(公告)日：2020-03-17

申请号：US16275380

申请日：2019-02-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/786 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-1th sub memory cell.

公开(公告)号：US10446583B2

公开(公告)日：2019-10-15

申请号：US15911233

申请日：2018-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/544 ,  H01L29/66

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

公开(公告)号：US10002648B2

公开(公告)日：2018-06-19

申请号：US15447809

申请日：2017-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Shuhei Nagatsuka

IPC: G11C11/40 ,  G11C7/06 ,  G11C5/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  H01L27/105

CPC classification number: G11C7/065 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A column driver includes an amplifier circuit for amplifying data of a read bit line and a latch circuit for retaining the amplified data. The latch circuit includes a pair of nodes Q and QB for retaining complementary data. Data is read from a memory cell in each write target row to a read bit line, and amplified by the amplifier circuit. The amplified data is written to the node Q (or QB) of the latch circuit. In a write target column, write data is input to the latch circuit through the node Q (or QB) to update data of the latch circuit. Then, in each column, data of the latch circuit is written to a write bit line, and the data of the write bit line is written to the memory cell.

公开(公告)号：US09911756B2

公开(公告)日：2018-03-06

申请号：US15245310

申请日：2016-08-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuto Yakubo ,  Shuhei Nagatsuka

IPC: H01L27/12 ,  H01L23/544 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.