公开(公告)号：US09159840B2

公开(公告)日：2015-10-13

申请号：US14456330

申请日：2014-08-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/10 ,  H01L29/41733 ,  H01L29/41775

Abstract: Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.

Abstract translation: 提供了即使在小型化时也具有大导通状态的晶体管的半导体装置。 晶体管包括在绝缘表面上的一对第一导电膜; 在一对第一导电膜上的半导体膜; 一对第二导电膜，其中一对第二导电膜中的一个和一对第二导电膜中的另一个分别连接到一对第一导电膜中的一个和一对第一导电膜中的另一个; 半导体膜上的绝缘膜; 以及设置在与绝缘膜上的半导体膜重叠的位置的第三导电膜。 此外，在半导体膜之上，第三导电膜插入在一对第二导电膜之间并远离一对第二导电膜。

公开(公告)号：US09117916B2

公开(公告)日：2015-08-25

申请号：US13646086

申请日：2012-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takehisa Hatano ,  Sachiaki Tezuka ,  Atsuo Isobe

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66969 ,  H01L21/0334 ,  H01L21/467 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/78603 ,  H01L29/7869

Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.

Abstract translation: 提供了一种小型化并且保持有利的特性的半导体器件。 此外，小型半导体器件具有高产率。 半导体器件具有包括设置在具有绝缘表面的衬底上的氧化物半导体膜的结构; 源极电极层和漏电极层，其设置成与氧化物半导体膜的侧表面接触并且具有比氧化物半导体膜的厚度大的厚度; 设置在所述氧化物半导体膜，所述源极电极层和所述漏极电极层上的栅极绝缘膜; 以及设置在由氧化物半导体膜的顶表面和源电极层和漏电极层的顶表面之间的台阶形成的凹陷部中的栅电极层。

公开(公告)号：US09105732B2

公开(公告)日：2015-08-11

申请号：US14483671

申请日：2014-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Toshinari Sasaki

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225

Abstract: To provide a transistor which includes an oxide semiconductor and is capable of operating at high speed or a highly reliable semiconductor device including the transistor, a transistor in which an oxide semiconductor layer including a pair of low-resistance regions and a channel formation region is provided over an electrode layer, which is embedded in a base insulating layer and whose upper surface is at least partly exposed from the base insulating layer, and a wiring layer provided above the oxide semiconductor layer is electrically connected to the electrode layer or a part of a low-resistance region of the oxide semiconductor layer, which overlaps with the electrode layer.

Abstract translation: 为了提供包括氧化物半导体并且能够高速运行的晶体管或包括晶体管的高度可靠的半导体器件，提供了包括一对低电阻区域和沟道形成区域的氧化物半导体层的晶体管 在基底绝缘层上嵌入并且其上表面至少部分地从基底绝缘层露出的电极层上，并且设置在氧化物半导体层上方的布线层电连接到电极层或电极层的一部分 氧化物半导体层的低电阻区域与电极层重叠。

公开(公告)号：US08916424B2

公开(公告)日：2014-12-23

申请号：US13755862

申请日：2013-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Atsuo Isobe ,  Kunio Hosoya

IPC: H01L21/00 ,  H01L21/02

CPC classification number: H01L29/66969 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/0237 ,  H01L21/02565 ,  H01L21/383 ,  H01L21/425 ,  H01L21/441 ,  H01L21/47573 ,  H01L27/10873 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/517 ,  H01L29/7869

Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.

Abstract translation: 为了提高包含氧化物半导体的晶体管的生产率，具有良好的电气特性。 在包括氧化物半导体膜上的栅绝缘膜和栅电极的顶栅晶体管中，在氧化物半导体膜上形成金属膜，向金属膜中添加氧以形成金属氧化物膜，并且金属氧化物 膜用作栅极绝缘膜。 在氧化物半导体膜上形成氧化物绝缘膜之后，可以在氧化物绝缘膜上形成金属膜。 向金属膜中添加氧以形成金属氧化物膜，并且还添加到氧化物半导体膜或氧化物绝缘膜。

公开(公告)号：US08873308B2

公开(公告)日：2014-10-28

申请号：US13923696

申请日：2013-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Atsuo Isobe ,  Yuji Iwaki ,  Koichiro Kamata ,  Yasuyuki Takahashi ,  Masumi Nomura

IPC: G11C14/00 ,  G11C29/00 ,  G11C5/06 ,  G11C5/14 ,  G11C16/30 ,  G06F1/32 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C16/30 ,  G06F1/3203 ,  G06F1/3275 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/20 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit that consumes less power by stop of supply of power for a short time. In a storage element, before supply of power is stopped, data in a first storage circuit is stored to a second storage circuit, and the data is read from the second storage circuit and a verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. After supply of power is restarted, the data in the second storage circuit is stored to the first storage circuit, and the verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. In such a manner, verification can be performed without requiring a time for verification.

Abstract translation: 信号处理电路通过在短时间内停止供电而消耗较少的功率。 在存储元件中，在停止供电之前，将第一存储电路中的数据存储到第二存储电路，并且从第二存储电路读取数据，并且验证电路可以确定第二存储电路中的数据 存储电路与第一存储电路中的数据匹配。 在重新开始供电之后，第二存储电路中的数据被存储到第一存储电路，并且验证电路可以确定第二存储电路中的数据是否与第一存储电路中的数据匹配。 以这种方式，可以执行验证，而不需要验证时间。

公开(公告)号：US20130221347A1

公开(公告)日：2013-08-29

申请号：US13777119

申请日：2013-02-26

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Atsuo Isobe ,  Sachiaki Tezuka ,  Shinji Ohno

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78603

Abstract: An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.

Abstract translation: 形成氧化物半导体层，在氧化物半导体层上形成栅极绝缘层，形成栅极层与氧化物半导体层重叠，栅极绝缘层插入其间，形成第一绝缘层以覆盖栅极 绝缘层和栅电极层，通过绝缘层引入杂质元素，以在氧化物半导体层中形成一对杂质区，在第一绝缘层，第一绝缘层和第二绝缘层上形成第二绝缘层 各层各向异性地蚀刻以形成与栅电极层的侧表面接触的侧壁绝缘层，并且形成与一对杂质区接触的源电极层和漏电极层。