公开(公告)号：US12040006B2

公开(公告)日：2024-07-16

申请号：US17815032

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Sheng-Chen Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

CPC classification number: G11C11/2257 ,  G11C11/223 ,  G11C11/2255 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20 ,  H10B51/30

Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.

公开(公告)号：US11968838B2

公开(公告)日：2024-04-23

申请号：US17460569

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/06 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H01L29/78391 ,  H10B51/10

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

公开(公告)号：US20240097010A1

公开(公告)日：2024-03-21

申请号：US18524417

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US11910616B2

公开(公告)日：2024-02-20

申请号：US17818562

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L29/417 ,  H01L23/535 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L23/535 ,  H01L29/41741 ,  H01L29/41775 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US11903216B2

公开(公告)日：2024-02-13

申请号：US17744212

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/32133 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H10B51/30

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US11862713B2

公开(公告)日：2024-01-02

申请号：US17815857

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L29/165

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20230387269A1

公开(公告)日：2023-11-30

申请号：US18359542

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L29/66803 ,  H01L29/42384 ,  H01L29/7851 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/02532 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L21/845

Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.

公开(公告)号：US11647634B2

公开(公告)日：2023-05-09

申请号：US17018114

申请日：2020-09-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H01L27/11 ,  H01L27/11597 ,  H01L29/78 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66

CPC classification number: H01L27/11597 ,  G11C5/06 ,  G11C11/223 ,  H01L21/8221 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US11600520B2

公开(公告)日：2023-03-07

申请号：US17159830

申请日：2021-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chia-Ta Yu ,  Han-Jong Chia

IPC: H01L21/768 ,  H01L29/24 ,  H01L27/1159 ,  H01L27/11597 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

公开(公告)号：US11574929B2

公开(公告)日：2023-02-07

申请号：US17113249

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/786

Abstract: A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.