公开(公告)号：US08422127B2

公开(公告)日：2013-04-16

申请号：US11886255

申请日：2006-03-17

Applicant: Shigeru Uchiyama ,  Takayuki Inoue ,  Masatoshi Okugawa

Inventor： Shigeru Uchiyama ,  Takayuki Inoue ,  Masatoshi Okugawa

IPC: G02B21/00

CPC classification number: G02B21/241 ,  G02B21/26 ,  G02B21/365

Abstract: The present invention relates to a microscopic image capturing apparatus having a structure that, in scanning an imageable area of an imaging unit in a predetermined direction in an imaging object area, in which a sample is present, can reliably set a focal point of the imaging unit on each imaging position set inside the imaging object area regardless of the type of focusing actuator. The microscopic image capturing apparatus has a sample setting stage having a sample setting surface that is inclined with respect to a scan plane orthogonal to an optical axis of an objective lens. By moving the sample setting stage along the scan plane such that the distance in the optical axis direction between the imaging unit and the sample setting surface varies monotonously, the focal point position of the imaging unit is adjusted in only one direction along the optical axis of the objective lens.

Abstract translation: 本发明涉及一种显微图像拍摄装置，其特征在于，在成像对象区域内，在成像对象区域内，在成像单元的预定方向的可成像区域中进行扫描时，能够可靠地设定成像的焦点 在成像对象区域内设置的每个成像位置上的单位，而与聚焦致动器的类型无关。 微观图像拍摄装置具有样品设定台，该样品设定台具有相对于与物镜的光轴正交的扫描面倾斜的样品设定面。 通过沿着扫描平面移动样品设定台，使得成像单元和样品设定面之间的光轴方向上的距离单调变化，则成像单元的焦点位置仅在沿着 物镜。

公开(公告)号：US20130009432A1

公开(公告)日：2013-01-10

申请号：US13637103

申请日：2011-03-31

Applicant: Takayuki Inoue

Inventor： Takayuki Inoue

IPC: B60N2/42 ,  B60N2/22

CPC classification number: B60N2/2356 ,  B60N2/4228 ,  B60N2/433 ,  B60N2205/50

Abstract: In a double-lock reclining seat, there is provided a mechanism for preventing two reclining lock mechanisms from being unlocked due to a collision load applied from a baggage or the like, without deforming the reclining lock mechanisms themselves, for example, without bending a connecting shaft of the two reclining lock mechanisms, or without adding any complicated mechanism changes to the interior of the reclining lock mechanisms. The double-lock reclining seat includes a load receiver 10 is fixed onto the connection shaft 5 of the two reclining lock mechanisms so as to extend obliquely downward from the rear side thereof, so that, as the load is applied to the back portion of the seat back from the baggage or the like, the load receiver 10 holds the connecting shaft 5 in a direction in which the two reclining lock mechanisms are locked.

Abstract translation: 在双锁躺椅中，提供了一种用于防止两个倾斜锁定机构由于从行李等施加的碰撞负载而被解锁的机构，而不会使倾斜锁定机构本身变形，例如，不会弯曲连接 两个倾斜锁定机构的轴，或者不会对倾斜锁定机构的内部增加任何复杂的机构变化。 双锁定倾斜座椅包括固定在两个倾斜锁定机构的连接轴5上的负载接收器10，以便从其后侧向下倾斜延伸，使得当负载施加到 从行李等座椅靠背，负载接收器10将连接轴5保持在两个倾斜锁定机构被锁定的方向上。

公开(公告)号：US08330887B2

公开(公告)日：2012-12-11

申请号：US12219020

申请日：2008-07-15

Applicant: Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takeshi Osada ,  Takayuki Inoue

Inventor： Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Takeshi Osada ,  Takayuki Inoue

IPC: G02F1/136

CPC classification number: G02F1/1368 ,  G02F1/133707 ,  G02F2201/40 ,  H01L27/1222 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

Abstract: It is an object to provide a liquid crystal display device and an electronic device of which aperture ratio increases. The present invention includes a substrate having an insulating surface, a transistor formed over the substrate, a pixel electrode electrically connected to the transistor. The transistor includes a gate electrode, a gate insulating layer over the gate electrode, a semiconductor layer having a microcrystalline structure over the gate insulating layer, and a buffer layer over the semiconductor layer having the microcrystalline structure. The channel width W of the transistor and the channel length L of the transistor satisfy a relation of 0.1≦W/L≦1.7.

Abstract translation: 本发明的目的是提供一种开口率增加的液晶显示装置和电子装置。 本发明包括具有绝缘表面的衬底，形成在衬底上的晶体管，电连接到晶体管的像素电极。 晶体管包括栅电极，栅电极上的栅极绝缘层，在栅极绝缘层上具有微晶结构的半导体层，以及在具有微晶结构的半导体层上的缓冲层。 晶体管的沟道宽度W和晶体管的沟道长度L满足关系式为0.1＆nlE; W / L＆nlE; 1.7。

公开(公告)号：US08305191B2

公开(公告)日：2012-11-06

申请号：US11802246

申请日：2007-05-21

Applicant: Hiroki Dembo ,  Yoshiyuki Kurokawa ,  Takayuki Inoue

Inventor： Hiroki Dembo ,  Yoshiyuki Kurokawa ,  Takayuki Inoue

IPC: H04Q5/22

CPC classification number: H01Q9/27 ,  G01S13/878 ,  G06K2017/0045 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1266 ,  H01L27/13 ,  H01Q1/40 ,  H01Q7/00

Abstract: A position detection system is formed by network connection of a plurality of interrogators and a server. An RFID and the interrogators communicate wirelessly, whereby a distance from each interrogator to the RFID is searched to search a position of the RFID from the distance. In order to calculate the distance from the interrogator to the RFID, a signal is oscillated with a frequency corresponding to amplitude of a signal received in the RFID from the interrogator. A frequency of a signal oscillated in the RFID is detected in the RFID or by the interrogator, whereby a distance from the interrogator to the RFID is detected.

Abstract translation: 通过多个询问器和服务器的网络连接形成位置检测系统。 RFID和询问器以无线方式进行通信，从而搜索从每个询问器到RFID的距离，以从远处搜索RFID的位置。 为了计算从询问器到RFID的距离，信号以对应于来自询问器的RFID中接收的信号的幅度的频率振荡。 在RFID中或由询问器检测到在RFID中振荡的信号的频率，从而检测到从询问器到RFID的距离。

公开(公告)号：US08258025B2

公开(公告)日：2012-09-04

申请号：US12848594

申请日：2010-08-02

Applicant: Shunpei Yamazaki ,  Yukie Suzuki ,  Yasuyuki Arai ,  Takayuki Inoue ,  Erumu Kikuchi

Inventor： Shunpei Yamazaki ,  Yukie Suzuki ,  Yasuyuki Arai ,  Takayuki Inoue ,  Erumu Kikuchi

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L21/02595 ,  C23C16/24 ,  C23C16/4404 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/5096 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32541 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

Abstract: A microcrystalline semiconductor film with high crystallinity is manufactured. In addition, a thin film transistor with excellent electric characteristics and high reliability, and a display device including the thin film transistor are manufactured with high productivity. A deposition gas containing silicon or germanium is introduced from an electrode including a plurality of projecting portions provided in a treatment chamber of a plasma CVD apparatus, glow discharge is caused by supplying high-frequency power, and thereby crystal particles are formed over a substrate, and a microcrystalline semiconductor film is formed over the crystal particles by a plasma CVD method.

Abstract translation: 制造具有高结晶度的微晶半导体膜。 此外，以高生产率制造具有优异的电特性和高可靠性的薄膜晶体管，以及包括薄膜晶体管的显示装置。 从设置在等离子体CVD装置的处理室中的多个突出部的电极引入含有硅或锗的沉积气体，通过供给高频电力而产生辉光放电，由此在基板上形成晶体粒子， 并且通过等离子体CVD法在晶体颗粒上形成微晶半导体膜。

公开(公告)号：US20120134508A1

公开(公告)日：2012-05-31

申请号：US13303783

申请日：2011-11-23

Applicant: Takayuki Inoue ,  Hiroshi Saruwatari ,  Kazunobu Kondo

Inventor： Takayuki Inoue ,  Hiroshi Saruwatari ,  Kazunobu Kondo

IPC: H04B15/00

CPC classification number: G10L21/0208 ,  G10L2021/02085 ,  G10L2021/02163

Abstract: An audio processing apparatus generates a suppression coefficient sequence that is composed of coefficient values corresponding to frequency components of an audio signal, the frequency components being multiplied by the corresponding coefficient values to suppress noise components of the audio signal. In the audio processing apparatus, a characteristic value calculation unit calculates a noise characteristic value depending on a shape of a magnitude distribution of the audio signal. An intensity setting unit variably sets a suppression intensity of the noise components based on the noise characteristic value. A coefficient sequence generation unit generates the suppression coefficient sequence based on the audio signal and the suppression intensity.

Abstract translation: 音频处理装置生成由与音频信号的频率分量对应的系数值构成的抑制系数序列，频率分量乘以相应的系数值，以抑制音频信号的噪声分量。 在音频处理装置中，特征值计算单元根据音频信号的幅度分布的形状来计算噪声特性值。 强度设定单元根据噪声特性值可变地设定噪声成分的抑制强度。 系数序列生成单元基于音频信号和抑制强度生成抑制系数序列。

公开(公告)号：US08163767B2

公开(公告)日：2012-04-24

申请号：US11995445

申请日：2006-07-13

Applicant: Takayuki Inoue ,  Takashi Tojo ,  Masataka Morita ,  Yutaka Nakajima ,  Keiko Hatanaka ,  Shohei Shirakami ,  Hiroshi Sasaki ,  Akira Tanaka ,  Fumie Takahashi ,  Koichiro Mukoyoshi ,  Yasuyuki Higashi ,  Akira Okimoto ,  Takeshi Hondo ,  Hitoshi Sawada

Inventor： Takayuki Inoue ,  Takashi Tojo ,  Masataka Morita ,  Yutaka Nakajima ,  Keiko Hatanaka ,  Shohei Shirakami ,  Hiroshi Sasaki ,  Akira Tanaka ,  Fumie Takahashi ,  Koichiro Mukoyoshi ,  Yasuyuki Higashi ,  Akira Okimoto ,  Takeshi Hondo ,  Hitoshi Sawada

IPC: A61K31/44 ,  C07D471/14

CPC classification number: C07D471/14 ,  C07D519/00

Abstract: The invention relates to compound of the formula (I) or its salt, wherein —R1, —R2, —R3, —R4, —R5, -M-, —X— and —Y═ are as defined in the description, their use of as, medicament, the process for their preparation and use for the treatment of JAK3 mediated diseases.

Abstract translation: 本发明涉及式（I）化合物或其盐，其中-R1，-R2，-R3，-R4，-R5，-M-，-X-和-Y =如说明书中所定义，它们 使用as，药物，其制备方法和用于治疗JAK3介导的疾病。

公开(公告)号：US20110315979A1

公开(公告)日：2011-12-29

申请号：US13164296

申请日：2011-06-20

Applicant: Masashi Tsubuku ,  Takayuki Inoue ,  Suzunosuke Hiraishi ,  Erumu Kikuchi ,  Hiromichi Godo ,  Shuhei Yoshitomi ,  Koki Inoue ,  Akiharu Miyanaga ,  Shunpei Yamazaki

Inventor： Masashi Tsubuku ,  Takayuki Inoue ,  Suzunosuke Hiraishi ,  Erumu Kikuchi ,  Hiromichi Godo ,  Shuhei Yoshitomi ,  Koki Inoue ,  Akiharu Miyanaga ,  Shunpei Yamazaki

IPC: H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/408

Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1

Abstract translation: 制造的是包括与氧化物半导体层的一部分重叠的氧化物半导体层，源极电极层和漏极电极层，与氧化物半导体层重叠的栅极绝缘层，源极电极层和漏极电极层的晶体管， 以及与所述氧化物半导体层的与氧化物半导体层的一部分重叠的栅电极，其间设置有栅极绝缘层，其中，在作为沟道形成区域的氧化物半导体层被照射光并停止光照射之后，弛豫时间 氧化物半导体层的光响应特性中的载流子具有至少两种模式：τ1和τ2，τ1<τ2，τ2为300秒以下。 此外，制造包括晶体管的半导体器件。

公开(公告)号：US20110227082A1

公开(公告)日：2011-09-22

申请号：US13048023

申请日：2011-03-15

Applicant: Takayuki Inoue ,  Masashi Tsubuku ,  Suzunosuke Hiraishi ,  Junichiro Sakata ,  Erumu Kikuchi ,  Hiromichi Godo ,  Akiharu Miyanaga ,  Shunpei Yamazaki

Inventor： Takayuki Inoue ,  Masashi Tsubuku ,  Suzunosuke Hiraishi ,  Junichiro Sakata ,  Erumu Kikuchi ,  Hiromichi Godo ,  Akiharu Miyanaga ,  Shunpei Yamazaki

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L31/032 ,  H01L31/18

Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time τ1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.

Abstract translation: “安全”陷阱存在的氧化物半导体层表现出光响应特性的两种模式。 通过使用氧化物半导体层，可以实现将光劣化抑制到最小并且电特性稳定的晶体管。 在光响应特性中表现出两种模式的氧化物半导体层具有1pA至10nA的光电流值。 当通过“安全”陷阱捕获载流子的平均时间τ1足够大时，光响应特性即电流值急剧下降的区域和电流值逐渐下降的区域有两种模式 在光电流随时间变化的结果中。

公开(公告)号：US07968880B2

公开(公告)日：2011-06-28

申请号：US12391398

申请日：2009-02-24

Applicant: Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

Inventor： Koji Dairiki ,  Takayuki Ikeda ,  Hidekazu Miyairi ,  Yoshiyuki Kurokawa ,  Hiromichi Godo ,  Daisuke Kawae ,  Takayuki Inoue ,  Satoshi Kobayashi

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/78618 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

Abstract: To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.

Abstract translation: 为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触 同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。