公开(公告)号：US06989323B2

公开(公告)日：2006-01-24

申请号：US10709314

申请日：2004-04-28

申请人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Bruce B. Doris ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823437 ,  H01L21/28097 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/4975

摘要： A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.

摘要翻译： 用于形成半导体器件的栅极结构的方法包括在衬底上限定导电牺牲结构，在导电牺牲结构的侧壁上形成反应的金属膜，以及去除导电牺牲结构的未反应部分。

公开(公告)号：US06489207B2

公开(公告)日：2002-12-03

申请号：US09871926

申请日：2001-06-01

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/223 ,  H01L21/2236 ,  H01L21/28035 ,  H01L21/28061 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823842

摘要： The present invention relates to a method of forming a very shallow source-drain (S/D) extension while simultaneously highly doping a very narrow polysilicon gate through to the gate dielectric interface. The invention also relates to the resulting semiconductor.

公开(公告)号：US06452265B1

公开(公告)日：2002-09-17

申请号：US09493929

申请日：2000-01-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Rosemary A. Previti-Kelly ,  Edmund Sprogis

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Rosemary A. Previti-Kelly ,  Edmund Sprogis

IPC分类号： H01L2334

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/3738 ,  H01L23/5389 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/0401

摘要： A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.

摘要翻译： 通过使支撑晶片上的预接线芯片对准并沉积具有接近芯片（例如硅，碳化硅，硅锗，锗或SiCGe）的热膨胀系数的非导电导热和非导电材料来构造多芯片模块 ）围绕芯片。 拆卸支撑晶片后，多芯片模块的处理通过多芯片模块和芯片表面的共享表面上的布线完成。

公开(公告)号：US06444402B1

公开(公告)日：2002-09-03

申请号：US09532187

申请日：2000-03-21

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L. Ma

IPC分类号： G03C500

CPC分类号： H01L21/31144 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76816

摘要： Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.

摘要翻译： 设计用于优化集成电路器件性能的两个或多个不同尺寸的特征通过将图案从具有抗蚀剂曝光工具优化的单个最小特征尺寸的特征的抗蚀剂转移到优选可溶性材料层而形成， 作为氧化锗。 然后使用阻挡掩模将该图案的部分放大，并且将所得到的图案优选地使用各向异性反应离子蚀刻转移到另一下层。 然后可以去除可溶性材料，留下具有不同特征尺寸的坚固的掩模，用于进一步处理。 优选地，通过提供绝缘体作为其他下层材料并用金属或其它导电材料填充开口来形成镶嵌导电线和通孔。

公开(公告)号：US06344416B1

公开(公告)日：2002-02-05

申请号：US09523480

申请日：2000-03-10

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21311

CPC分类号： H01L22/20 ,  C23C16/04 ,  C23C16/513 ,  C23C16/52 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76229 ,  H01L21/8234 ,  Y10S438/911

摘要： Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film. Because the semiconductor film has variations between the devices, device characteristics of the devices should be different. By measuring the device characteristics of devices having the variations, the device with the optimum device characteristic may be chosen, thereby indicating the appropriate semiconductor film thickness and/or composition. Moreover, small production runs of the same devices, having different characteristics, will allow the end user to select the appropriate devices for their needs.

摘要翻译： 公开了可以在半导体制造期间引入有意的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产运行的方法和装置。 本发明径向地改变半导体膜的厚度和/或组成，以补偿半导体膜中已知的半导体膜的径向变化，这是通过在半导体膜上进行随后的半导体处理步骤引起的。另外，公开了可以 引入有意识的半导体薄膜变化以确定最佳的器件特性或产生小的生产运行。 引入半导体薄膜变化，例如厚度变化和/或组成变化，允许制造不同的装置。 可以制造多个器件，其具有半导体膜的变化。 因为半导体薄膜在器件之间有变化，所以器件的器件特性应该是不同的。 通过测量具有变化的器件的器件特性，可以选择具有最佳器件特性的器件，从而指示适当的半导体膜厚度和/或组成。 此外，相同设备的小生产运行具有不同的特性，将允许最终用户根据需要选择适当的设备。

公开(公告)号：US06333229B1

公开(公告)日：2001-12-25

申请号：US09523839

申请日：2000-03-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4925 ,  H01L29/7834

摘要： A viable T-gate FET is produced even when the cap of the “T” is mis-aligned from the stem of the “T”. A subtractive etch is used to selectively etch the material forming the cap of the T-gate and the material forming the stem of the T-gate in order to avoid the etching away of portions of the stem if the cap is mis-aligned relative to the stem. To that end, germanium (Ge) may be used as the material for the cap of the T-gate and poly silicon (polySi) may be used as the material for the stem of the T-gate. Since germanium can be etched selectively relative to silicon from 10:1 to as much as 20:1, the cap of the T can be formed without appreciable damage to the stem portion and thus without damage to the resultant FET device.

摘要翻译： 即使当“T”的盖与“T”的杆不对齐时，也会产生可行的T型栅极FET。 使用减法蚀刻来选择性地蚀刻形成T形栅的帽和形成T形栅的杆的材料的材料，以避免如果帽相对于 茎。 为此，可以使用锗（Ge）作为T型栅极的盖的材料，并且可以使用多晶硅（polySi）作为T型栅极的材料。 由于锗可以相对于硅选择性地从10:1蚀刻到多达20:1，所以可以形成T的帽，而不会对柄部产生明显的损害，从而不会损坏所得到的FET器件。

公开(公告)号：US5998835A

公开(公告)日：1999-12-07

申请号：US24840

申请日：1998-02-17

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Jack A. Mandelman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma ,  Jack A. Mandelman

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/78 ,  H01L29/50

CPC分类号： H01L29/66613 ,  H01L29/66621 ,  H01L29/7834 ,  H01L21/2255

摘要： A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.

摘要翻译： 一种MOSFET器件及其制造方法。 该器件具有形成在硅衬底中的沟槽。 设备的通道位于沟槽的底部。 扩散层邻近沟槽的相对侧形成。 通过沿着沟槽的侧壁和沟槽的一部分延伸扩散层，将每个扩散层连接到器件沟道的边缘。

公开(公告)号：US07838943B2

公开(公告)日：2010-11-23

申请号：US11161146

申请日：2005-07-25

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Mark E. Masters

IPC分类号： H01L21/70

CPC分类号： H01L21/823412 ,  B01J23/74 ,  B01J37/0238 ,  B82Y10/00 ,  H01L21/7624 ,  H01L21/823437 ,  H01L27/286 ,  H01L51/0048 ,  H01L51/0545 ,  H01L51/055 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/763

摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.

摘要翻译： 在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。 所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管 晶体管位于至少一个平面半导体器件的栅极之上。

公开(公告)号：US07601205B2

公开(公告)日：2009-10-13

申请号：US12125442

申请日：2008-05-22

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： B03C3/60

CPC分类号： B03C3/41 ,  B03C3/60 ,  B03C2201/10 ,  Y10S977/742

摘要： An air particle precipitator and a method of air filtration include a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further includes an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further include a metal layer over the carbon nanotube.

摘要翻译： 空气颗粒除尘器和空气过滤方法包括壳体单元; 住房单元中的第一个导体; 壳体单元中的第二导体; 和在第二导体上生长的碳纳米管。 优选地，第一导体与第二导体相对定位。 空气粒子除尘器还包括适于向壳体单元施加电场的电场源。 此外，碳纳米管适于使壳体单元中的气体电离，其中电离气体对位于壳体单元中的气体微粒进行充电，并且其中第一导体适于捕集带电气体微粒。 空气粒子沉淀器还可以包括在碳纳米管上的金属层。

公开(公告)号：US07528494B2

公开(公告)日：2009-05-05

申请号：US11266456

申请日：2005-11-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L21/4763

CPC分类号： H01L29/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

摘要： A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

摘要翻译： 制造三维集成电路芯片或晶片组件的过程，更具体地说，在将芯片定向成堆叠之前，将其布置在晶片上的处理。 还公开了三维集成电路的制造，其中芯片密度可以非常高并且在晶片仍然完整且通常为平面结构的情况下被处理。