公开(公告)号：US08377632B2

公开(公告)日：2013-02-19

申请号：US13118447

申请日：2011-05-29

申请人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G03F7/26

CPC分类号： H01L21/3083

摘要： The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.

摘要翻译： 本发明提供一种通过使用光致抗蚀剂层作为缓冲液来减少微载物效应的方法。 该方法包括：提供限定有致密区域和隔离区域的衬底。 然后，分别在密集区域和孤立区域上形成致密特征图案和隔离特征图案。 之后，形成光致抗蚀剂层以覆盖隔离区域。 最后，通过将密集特征图案和孤立的特征图案作为掩模来蚀刻基底和光致抗蚀剂层。

公开(公告)号：US20130017687A1

公开(公告)日：2013-01-17

申请号：US13183358

申请日：2011-07-14

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/306

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

摘要翻译： 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US08335119B1

公开(公告)日：2012-12-18

申请号：US13276952

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G11C7/00

CPC分类号： H01L27/10847 ,  G11C11/40 ,  G11C29/50016 ,  G11C2029/0403 ,  H01L22/12 ,  H01L22/20 ,  H01L27/10861

摘要： A method of inspecting a memory cell is provided, including: providing a semiconductor substrate with a capacitor formed therein and a transistor formed thereon, wherein the transistor is electrically connected to the capacitor; inspecting a size of a top surface of the capacitor and a pitch between the capacitor and the transistor electrically connected thereto by an optical measuring system, thereby obtaining a first measurement data and a second measurement data; and comparing the first and second measurement data with designed specifications of the capacitor and transistor, thereby determining functionality of the memory cell comprising the capacitor and the transistor.

摘要翻译： 提供了一种检查存储单元的方法，包括：提供其中形成有电容器的半导体衬底和形成在其上的晶体管，其中晶体管电连接到电容器; 通过光学测量系统检查电容器的顶表面的大小和电容器与与其电连接的晶体管之间的间距，从而获得第一测量数据和第二测量数据; 以及将第一和第二测量数据与电容器和晶体管的设计规范进行比较，从而确定包括电容器和晶体管的存储单元的功能。

公开(公告)号：US20120289133A1

公开(公告)日：2012-11-15

申请号：US13106822

申请日：2011-05-12

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B24B55/00

CPC分类号： H01L21/02057 ,  B24B37/34 ,  B24B57/02 ,  H01L21/67046

摘要： A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface.

摘要翻译： 化学机械抛光（CMP）系统包括生产所用浆料的晶片抛光单元; 用于接收和处理所使用的浆料从而产生提取的碱性溶液的浆料处理系统; 以及利用所提取的碱性溶液洗涤抛光的晶片表面的后CMP清洁单元。 后CMP清洁单元包括用于支撑和旋转晶片的多个辊，用于洗涤晶片的刷子和布置在刷子附近的喷杆，用于将提取的碱性溶液喷射到抛光的晶片表面上。

公开(公告)号：US20120287500A1

公开(公告)日：2012-11-15

申请号：US13106864

申请日：2011-05-13

申请人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Ming-Teng Hsieh ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G02B21/02 ,  G02B3/02

CPC分类号： G02B5/005 ,  G02B21/02

摘要： An optical lens is provided in the present invention. The optical lens includes a first curved surface and an annular mask component on and in direct contact with the first curved surface, wherein the annular mask component shields a peripheral annular region of the optical lens from entry of light. The present invention further provides an optical microscope system using the same.

摘要翻译： 在本发明中提供了一种光学透镜。 光学透镜包括在第一弯曲表面上且与第一弯曲表面直接接触的第一弯曲表面和环形掩模部件，其中环形掩模部件屏蔽光学透镜的外围环形区域以防止光入射。 本发明还提供一种使用其的光学显微镜系统。

公开(公告)号：US20120286402A1

公开(公告)日：2012-11-15

申请号：US13105910

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/06 ,  H01L21/302 ,  H01L23/48

CPC分类号： H01L21/0337 ,  B81B2203/0361 ,  B81B2203/0392 ,  B81C1/00103 ,  H01L21/0338 ,  H01L21/28123

摘要： A cuboidal protuberant structure is provided. The cuboidal protuberant structure includes a substrate and a protrusion disposed on the substrate. The protrusion has a vertical side wall with a rounded corner, a protuberant width and a protuberant length. At least one of the protuberant width and the protuberant length is not greater than 33 nm.

摘要翻译： 提供立方形隆起结构。 立方体隆起结构包括基板和设置在基板上的突起。 突起具有垂直侧壁，其具有圆角，突出宽度和突出长度。 突出宽度和突出长度中的至少一个不大于33nm。

公开(公告)号：US20120286353A1

公开(公告)日：2012-11-15

申请号：US13106852

申请日：2011-05-12

申请人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

摘要： A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

摘要翻译： 公开了一种沟槽MOS结构。 沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 沟槽栅极部分地设置在掺杂区域中。 沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。 两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

公开(公告)号：US08309467B2

公开(公告)日：2012-11-13

申请号：US12962666

申请日：2010-12-08

申请人： Chien-Mao Liao ,  Yi-Nan Chen

发明人： Chien-Mao Liao ,  Yi-Nan Chen

IPC分类号： H01L21/306 ,  B44C1/22

CPC分类号： H01L21/321 ,  H01L21/3105 ,  H01L21/76819 ,  H01L21/7684

摘要： A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

摘要翻译： 提供了一种装置的制造方法。 在制造方法中，设置有基板。 基板具有多个图案和形成在其上的多个开口，并且开口位于图案之间。 在图案上形成第一液体支撑层，并且用第一液体支撑层填充开口。 将第一液体支撑层转变成第一固体支撑层。 第一固体支持层包括形成在开口中的多个支撑元件，并且支撑元件形成在图案之中。 对图案进行处理。 包括支撑元件的第一固体支持层被转化成第二液体支撑层。 第二液体支撑层被去除。

公开(公告)号：US08252684B1

公开(公告)日：2012-08-28

申请号：US13118480

申请日：2011-05-30

申请人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Hsiu-Chun Lee ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/44 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3081 ,  H01L21/3212

摘要： A method of forming a trench by a silicon-containing mask is provided in the present invention. The method includes providing a substrate covered with a silicon-containing mask. Then, anti-etch dopants are implanted into the silicon-containing mask to transform the silicon-containing mask into an etching resist mask. Later, the substrate and the etching resist mask are patterned to form at least one trench. Next, a silicon-containing layer is formed to fill into the trench. Finally, the silicon-containing layer is etched by taking the etching resist mask as a mask.

摘要翻译： 在本发明中提供了通过含硅掩模形成沟槽的方法。 该方法包括提供用含硅掩模覆盖的基底。 然后，将抗蚀刻掺杂剂注入到含硅掩模中以将含硅掩模转变成抗蚀剂掩模。 然后，对衬底和抗蚀剂掩模进行构图以形成至少一个沟槽。 接下来，形成含硅层以填充到沟槽中。 最后，通过将抗蚀剂掩模作为掩模来蚀刻含硅层。

公开(公告)号：US20070020844A1

公开(公告)日：2007-01-25

申请号：US11490206

申请日：2006-07-19

申请人： Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10888 ,  H01L27/10885

摘要： A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer. The remaining polysilicon masking layer is completely transformed into a metal polycide layer and then removed. A method for fabricating a bit line of a memory device is also disclosed.

摘要翻译： 一个镶嵌过程。 提供了由电介质层覆盖的衬底和具有暴露下面介电层的开口的上覆多晶硅掩模层。 蚀刻暴露的介电层以在其中形成镶嵌开口，并且一部分多晶硅掩模层保留在电介质层上。 剩余的多晶硅掩模层完全转变为金属多晶硅化物层，然后除去。 还公开了一种用于制造存储器件的位线的方法。