公开(公告)号：US20210050438A1

公开(公告)日：2021-02-18

申请号：US16578407

申请日：2019-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

公开(公告)号：US10692777B2

公开(公告)日：2020-06-23

申请号：US16053737

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/324 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

公开(公告)号：US20190157445A1

公开(公告)日：2019-05-23

申请号：US16253158

申请日：2019-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/78 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first spacer adjacent to the first fin-shaped structure and a second spacer adjacent to the second fin-shaped structure; and using the first spacer and the second spacer as mask to remove part of the substrate for forming a third fin-shaped structure on the first region and a fourth fin-shaped structure on the second region, in which the third fin-shaped structure includes a first top portion and a first bottom portion and the fourth fin-shaped structure includes a second top portion and a second bottom portion;

公开(公告)号：US20190140068A1

公开(公告)日：2019-05-09

申请号：US16239541

申请日：2019-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40

Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.

公开(公告)号：US20190019875A1

公开(公告)日：2019-01-17

申请号：US15678125

申请日：2017-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Cheng-Ping Kuo ,  Kuan-Hao Tseng

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.

公开(公告)号：US20180342426A1

公开(公告)日：2018-11-29

申请号：US16053737

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7851

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

公开(公告)号：US10032672B1

公开(公告)日：2018-07-24

申请号：US15666583

申请日：2017-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Shih-Hung Tsai ,  Chorng-Lih Young

IPC: H01L21/82 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device includes the following steps: providing a semiconductor substrate having a first fin; forming a first set of gate structures on the first fin, where the gate structures are surrounded by an interlayer dielectric; forming a first contact hole in the interlayer dielectric between two adjacent gate structures; forming a first dopant source layer on the bottom of the first contact hole, where the dopant source layer comprise dopants with a first conductivity type; and annealing the first dopant source layer to diffuse the dopants out of the first dopant source layer.

公开(公告)号：US20180197981A1

公开(公告)日：2018-07-12

申请号：US15916261

申请日：2018-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, wherein the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

公开(公告)号：US20170278947A1

公开(公告)日：2017-09-28

申请号：US15196024

申请日：2016-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed therebetween. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region. The present invention further provides a semiconductor fin structure.

公开(公告)号：US20170263732A1

公开(公告)日：2017-09-14

申请号：US15481419

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Yi-Fan Li ,  Kun-Hsin Chen ,  Tong-Jyun Huang ,  Jyh-Shyang Jenq ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26546 ,  H01L29/1054 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.