公开(公告)号：US06440797B1

公开(公告)日：2002-08-27

申请号：US09966702

申请日：2001-09-28

申请人： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

发明人： Yider Wu ,  Jean Yee-Mei Yang ,  Mark Ramsbey ,  Emmanuel H. Lingunis ,  Yu Sun

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.

摘要翻译： 一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在所述氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。 本发明还涉及包括氮化物阻挡层的SONOS型器件。

公开(公告)号：US06232646B1

公开(公告)日：2001-05-15

申请号：US09082607

申请日：1998-05-20

申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

IPC分类号： H01L2900

CPC分类号： H01L21/7621 ,  H01L21/76232

摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

公开(公告)号：US06034394A

公开(公告)日：2000-03-07

申请号：US992950

申请日：1997-12-18

申请人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

发明人： Mark Ramsbey ,  Tuan D. Pham ,  Yu Sun ,  Kenneth W. Au

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

摘要翻译： 提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。 通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。 改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。 控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。 裂纹通常发生在半导体器件的随后热处理期间。 因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

公开(公告)号：US5999452A

公开(公告)日：1999-12-07

申请号：US63688

申请日：1998-04-21

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US5981364A

公开(公告)日：1999-11-09

申请号：US568195

申请日：1995-12-06

申请人： Mark T. Ramsbey ,  Hsingya Arthur Wang ,  Yu Sun

发明人： Mark T. Ramsbey ,  Hsingya Arthur Wang ,  Yu Sun

IPC分类号： H01L21/28 ,  H01L29/49

CPC分类号： H01L21/28035 ,  H01L29/4925

摘要： Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.

摘要翻译： 本文公开了一种在硅器件的硅衬底上形成硅栅叠层的方法。 形成硅栅极堆叠的方法包括以下步骤：在硅衬底上生长氧化物层，沉积薄层的硅以在氧化物层上形成薄的硅层，在薄层上沉积厚的硅层 硅，并且将杂质引入仅硅的厚层中以形成硅栅极，由此硅栅极包括硅的薄层和具有杂质的厚的硅层。 引入浓度的杂质，杂质浓度和厚层厚度在施加硅栅堆叠周围的保护性屏蔽氧化物层时阻碍氧化层侵入硅栅中。

公开(公告)号：US5966618A

公开(公告)日：1999-10-12

申请号：US36288

申请日：1998-03-06

申请人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

发明人： Yu Sun ,  Tuan D. Pham ,  Mark T. Ramsbey ,  Chi Chang

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L27/08 ,  H01L27/105

CPC分类号： H01L21/76221 ,  H01L27/105

摘要： A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.

摘要翻译： 提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。 在闪速存储器件的核心区域中提供了薄的LOCOS结构，并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。 设备和过程不容易受到“赛道”问题，“氧化物”碰撞问题和“纵梁”问题的影响。 该方法利用两个分开的氮化物或硬掩模层。

公开(公告)号：US5912489A

公开(公告)日：1999-06-15

申请号：US940674

申请日：1997-09-30

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US20220235204A1

公开(公告)日：2022-07-28

申请号：US17583632

申请日：2022-01-25

申请人： Li Jia ,  Yu Sun

发明人： Li Jia ,  Yu Sun

IPC分类号： C08L9/00

摘要： A curable rubber composition including a rubber, a plurality of ground particles, and a reactive surfactant represented by the formula: X—Y—Z where X is a reactive group capable of forming covalent links with the rubber during compounding or vulcanization, Y is a hydrophobic linkage, and Z is a polar group capable of forming self-assemblies via intermolecular interactions, and wherein the reactive surfactant is incompatible with the rubber and a method of making the same.

公开(公告)号：US11331724B2

公开(公告)日：2022-05-17

申请号：US17280025

申请日：2019-09-25

申请人： Xiaoming Wang ,  Yang Zhao ,  Wenyu Wang ,  Qing Chang ,  Zhiqiang Ren ,  Guofeng Han ,  Sheng Zhu ,  Jing Shi ,  Tao Teng ,  Yu Sun ,  Zhiyong Qin ,  DALIAN UNIVERSITY OF TECHNOLOGY

发明人： Xiaoming Wang ,  Yang Zhao ,  Wenyu Wang ,  Wei Dong ,  Yao Meng ,  Qing Chang ,  Zhiqiang Ren ,  Jing Shi ,  Guofeng Han ,  Sheng Zhu ,  Tao Teng ,  Fumin Xu ,  Zhaofeng Bai ,  Yanyang Wang ,  Yang Han ,  Guobin Li ,  Yu Sun ,  Zhiyong Qin

IPC分类号： B22F9/10 ,  B22F1/065 ,  C22C13/00

摘要： An apparatus efficiently preparing ultrafine spherical metal powder includes a housing, a crucible and a powder collection area arranged in the housing. The turnplate arranged in the powder collection area is an inlaid structure. The part inlaid into the body part acts as an atomization plane of the turnplate. The atomization plane is provided with a concentric circular groove, and the turnplate is provided with an air hole. The apparatus is used for preparing ultrafine spherical metal powder by on-by-one droplets centrifugal atomization method, mainly combining the uniform droplet jet method and the centrifugal atomization method, which breaks through the traditional metal splitting model, makes the molten metal in a fibrous splitting, so as to efficiently prepare ultrafine spherical metal powder with narrow particle size distribution interval, high sphericity, good flowability, excellent spreadability, uniform and controllable size, no satellite droplets and suitable for industrial production.

公开(公告)号：US09744672B2

公开(公告)日：2017-08-29

申请号：US14355347

申请日：2012-11-16

申请人： Yu Sun ,  Michael David Coovert ,  Ivan Shindev

发明人： Yu Sun ,  Michael David Coovert ,  Ivan Shindev

IPC分类号： G06G7/48 ,  B25J11/00 ,  G05D1/02 ,  B25J9/16

CPC分类号： B25J11/0005 ,  B25J9/1674 ,  G05B2219/40196 ,  G05B2219/40202 ,  G05B2219/40414 ,  G05D1/0246 ,  G05D1/0274

摘要： In one embodiment, communicating robot intentions to human beings involves determining movements that a robot will make to complete a task, visually communicating a long-term intention of the robot that provides an indication of the movements the robot will make in completing the task, and visually communicating a short-tem intention of the robot that provides an indication of a movement of the robot will make within the next few seconds in working toward completing the task.