公开(公告)号：US08426298B2

公开(公告)日：2013-04-23

申请号：US13113530

申请日：2011-05-23

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

Abstract: A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

Abstract translation: 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源/漏延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US08084305B2

公开(公告)日：2011-12-27

申请号：US12036616

申请日：2008-02-25

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

公开(公告)号：US08039284B2

公开(公告)日：2011-10-18

申请号：US11640713

申请日：2006-12-18

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L21/00 ,  H01L29/84

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

Abstract translation: 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US07667247B2

公开(公告)日：2010-02-23

申请号：US11745862

申请日：2007-05-08

Applicant: Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

Inventor： Ching-Ya Wang ,  Wen-Chin Lee ,  Denny Tang

IPC: H01L29/80 ,  H01L31/112

CPC classification number: H01L21/28185 ,  H01L21/2822 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成电介质层，用含碳基团处理电介质层，在经处理的电介质层上形成导电层，以及图案化和蚀刻电介质层和导电层以形成 门结构。 含碳基团包括OCH 3或CN物质。

公开(公告)号：US07646068B2

公开(公告)日：2010-01-12

申请号：US11483913

申请日：2006-07-10

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Abstract translation: 半导体芯片包括其中设置有第一和第二有源区的半导体衬底126。 电阻器124形成在第一有源区域中，并且电阻器124包括形成在两个端子136之间的掺杂区域128.应变沟道晶体管132形成在第二有源区域中。 该晶体管包括第一和第二应力源141，该第一和第二应力器141形成在与基片相反的相邻的应变通道区域143之间。

公开(公告)号：US07569896B2

公开(公告)日：2009-08-04

申请号：US11438711

申请日：2006-05-22

Applicant: Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

Abstract: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.

Abstract translation: 提供了在通道区​​域中具有优化的应力的MOS器件及其形成方法。 MOS器件包括在衬底上的栅极，栅极侧壁上的栅极间隔物，其中在栅极间隔物下方存在非硅化物区域，在衬底中包含凹陷的源极/漏极区域和源极上的硅化物区域 /漏区。 在硅化物区域的较高部分和硅化物区域的下部之间形成台阶高度。 凹槽与非硅化物区域的相应边缘间隔一定距离。 台阶高度和间距优选具有小于或等于约3的比率。非硅化物区域的宽度和台阶高度优选具有小于或等于约3的比率。MOS器件优选为 NMOS器件。

公开(公告)号：US20090078578A1

公开(公告)日：2009-03-26

申请号：US12195844

申请日：2008-08-21

Applicant: Cheng-Hsien Lin ,  Yao-Wen Bai ,  Rui Zhang ,  Wen-Chin Lee

Inventor： Cheng-Hsien Lin ,  Yao-Wen Bai ,  Rui Zhang ,  Wen-Chin Lee

IPC: H05K3/00 ,  B82B3/00

CPC classification number: H05K3/424 ,  B82Y10/00 ,  C23C18/1204 ,  C23C18/127 ,  C23C18/1287 ,  H05K3/427 ,  H05K2201/026 ,  H05K2201/0323

Abstract: A pre-plating solution for making a printed circuit board includes carbon nanotubes of 0.01-3 wt %, a surfactant of 0.01-4 wt %, an alkaline substance of 0.01-l wt % and a solvent. A method for preparing a pre-plating solution comprising the steps of: providing a plurality of carbon nanotubes; purifying the carbon nanotubes; treating the purified carbon nanotubes with an acid; mixing the treated carbon nanotubes, an alkaline substance and a solvent to form suspension; and adding surfactant into suspension.

Abstract translation: 用于制造印刷电路板的预镀溶液包括0.01-3重量％的碳纳米管，0.01-4重量％的表面活性剂，0.01-1重量％的碱性物质和溶剂。 一种制备预镀液的方法，包括以下步骤：提供多个碳纳米管; 纯化碳纳米管; 用酸处理纯化的碳纳米管; 混合处理的碳纳米管，碱性物质和溶剂以形成悬浮液; 并将表面活性剂加入悬浮液中。

公开(公告)号：US20090045411A1

公开(公告)日：2009-02-19

申请号：US11839352

申请日：2007-08-15

Applicant: Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Hong-Nien Lin ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/24 ,  H01L29/778

CPC classification number: H01L29/7833 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate; an insulating region extending from substantially a top surface of the semiconductor substrate into the semiconductor substrate; an embedded dielectric spacer adjacent the insulating region, wherein a bottom of the embedded dielectric spacer adjoins the semiconductor substrate; and a semiconductor material adjoining a top edge and extending on a sidewall of the embedded dielectric spacer.

Abstract translation: 提供半导体结构。 半导体结构包括半导体衬底; 绝缘区域，其从所述半导体衬底的大致顶表面延伸到所述半导体衬底中; 邻近所述绝缘区域的嵌入式电介质间隔件，其中所述嵌入式电介质间隔件的底部邻接所述半导体衬底; 以及邻接在顶部边缘并且在嵌入的电介质间隔物的侧壁上延伸的半导体材料。

公开(公告)号：US07459756B2

公开(公告)日：2008-12-02

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US07453133B2

公开(公告)日：2008-11-18

申请号：US10880992

申请日：2004-06-30

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L27/095

CPC classification number: H01L23/3192 ,  H01L23/485 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract translation: 本发明的优选实施方案包括介电/金属/第二能带隙（E />）半导体/第一电极 g 衬底结构。 为了降低接触电阻，将具有较低能量带隙（2Ω）的半导体与金属接触。 第二个和第二个半导体的能带隙比第一个第二半导体的能量带隙低， 半导体，优选低于1.1eV。 此外，可以在金属上沉积介电层。 电介质层具有内置应力以补偿金属，第二和第二半导体中的应力， g 衬底。 还公开了制造该结构的过程。