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161 条记录 (耗时 0.031 秒)

    Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same
    71.
    发明申请
    Floating gate, a nonvolatile memory device including the floating gate and method of fabricating the same 审中-公开
    浮动栅极，包括浮动栅极的非易失性存储器件及其制造方法

    公开(公告)号：US20070200165A1

    公开(公告)日：2007-08-30

    申请号：US11656454

    申请日：2007-01-23

    申请人： Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Jung-Ho Moon ,  Soung-Youb Ha ,  Byeong-Cheol Lim

    发明人： Young-Cheon Jeong ,  Chul-Soon Kwon ,  Jae-Min Yu ,  Jae-Hyun Park ,  Jung-Ho Moon ,  Soung-Youb Ha ,  Byeong-Cheol Lim

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

    摘要： Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.

    摘要翻译： 示例性实施例可以提供非易失性存储器件。 示例性实施例非易失性存储器件可以包括形成在半导体衬底上的浮置栅极结构，其间具有栅极绝缘层和/或与浮置栅极相邻形成的控制栅极，在它们之间具有隧道绝缘层。 浮置栅极可以包括形成在栅极绝缘层上的第一浮动栅极，形成在第一浮动栅极上的第二浮置栅极，其间具有第一绝缘图案，和/或形成在第一浮动栅极的至少一个侧壁上的栅极连接层 绝缘图案，使得栅极导电层可以电连接第一浮动栅极和第二浮动栅极。 第二浮栅可以在其纵向端形成有可能不接触栅极连接层的尖端。

    Method of fabricating a flash memory cell
    73.
    发明授权
    Method of fabricating a flash memory cell 有权
    制造闪存单元的方法

    公开(公告)号：US07205194B2

    公开(公告)日：2007-04-17

    申请号：US10874579

    申请日：2004-06-24

    申请人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    发明人： Yong-Sun Lee ,  Jae-Min Yu ,  Don-Woo Lee ,  Jung-Hun Cho ,  Chul-Soon Kwon ,  Jung-Ho Moon ,  In-Gu Yoon ,  Jae-Hyun Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

    摘要： A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

    摘要翻译： 一种制造具有分裂栅极结构的闪存单元的方法。 牺牲层形成在形成在半导体衬底上的浮栅上。 牺牲层被蚀刻以形成暴露浮动栅极层的一部分的开口。 在开口内部形成栅极层间绝缘层图案。 在去除牺牲层图案并蚀刻浮栅（使用栅极层间绝缘层图案作为蚀刻掩模）之后，在栅极层间绝缘层图案下方形成浮栅。 控制栅极形成为与浮置栅极的一部分重叠。

    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same
    74.
    发明申请
    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
    具有多个有序区域的垂直位置的PRAM及其形成方法

    公开(公告)号：US20060076548A1

    公开(公告)日：2006-04-13

    申请号：US11246863

    申请日：2005-10-07

    申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

    摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

    摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device
    75.
    发明申请
    Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device 失效
    具有分裂栅电极结构的半导体器件和用于制造半导体器件的方法

    公开(公告)号：US20060027858A1

    公开(公告)日：2006-02-09

    申请号：US11246590

    申请日：2005-10-11

    申请人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    发明人： Jung-Ho Moon ,  Jae-Min Yu ,  Don-Woo Lee ,  Chul-Soon Kwon ,  In-Gu Yoon ,  Yong-Sun Lee ,  Jae-Hyun Park

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11539

    摘要： A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

    摘要翻译： 半导体器件包括分为存储单元区域和逻辑区域的衬底。 在基板的存储单元区域中形成分割栅电极结构。 在分离栅电极结构的侧壁和基板的表面上形成氧化硅层。 在位于分离栅电极结构的侧壁上的氧化硅层上形成字线。 字线具有上宽度和下宽度。 较低的宽度大于上部宽度。 在基板的逻辑区域上形成逻辑门图案。 逻辑门图案具有比字线的较低宽度更薄的厚度。

    Phase change memory device and method for forming the same
    76.
    发明申请
    Phase change memory device and method for forming the same 有权
    相变存储器件及其形成方法

    公开(公告)号：US20060011902A1

    公开(公告)日：2006-01-19

    申请号：US11149755

    申请日：2005-06-10

    申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

    摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

    摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

    Data packet re-sequencer
    79.
    发明授权
    Data packet re-sequencer 有权
    数据包重新排序器

    公开(公告)号：US06434148B1

    公开(公告)日：2002-08-13

    申请号：US09467684

    申请日：1999-12-21

    申请人： Jae-Hyun Park

    发明人： Jae-Hyun Park

    IPC分类号： H04L1228

    CPC分类号： H04L12/5601 ,  H04L2012/565 ,  H04L2012/5674

    摘要： A cell re-sequencer for re-sequencing the cells switched by an ATM switching system, comprises a maximum delay register for setting the maximum delay value by initialization to output the maximum delay value according to internal clock pulses, a base address increment register for increasing the initial value of the initialization set as a base address one by one according to cell time clock pulses, a delay detector for detecting the real delay of a cell from its header, a cell storing address generator for adding the base address to the delay difference between the maximum delay and real delay to generate a cell storing address, a multiplexer for multiplexing the base address and cell storing address according to the cell time clock pulses, and a memory address register for temporarily storing the output of the multiplexer.

    摘要翻译： 用于重新排序由ATM交换系统切换的小区的小区重新定序器包括最大延迟寄存器，用于通过初始化设置最大延迟值，以根据内部时钟脉冲输出最大延迟值，基地址递增寄存器，用于增加 基于单元时钟脉冲将初始化设置为基地址的初始值，一个用于从其报头检测单元的实际延迟的延迟检测器，用于将基址添加到延迟差的单元存储地址发生器 在最大延迟和实际延迟之间产生单元存储地址，多路复用器，用于根据单元时钟脉冲多路复用基地址和单元存储地址;以及存储器地址寄存器，用于临时存储多路复用器的输出。

    Method for etching oxide film in plasma etching system
    80.
    发明授权
    Method for etching oxide film in plasma etching system 失效
    在等离子体蚀刻系统中蚀刻氧化膜的方法

    公开(公告)号：US6103137A

    公开(公告)日：2000-08-15

    申请号：US27808

    申请日：1998-02-23

    申请人： Jae-Hyun Park

    发明人： Jae-Hyun Park

    IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/336 ,  H01L29/78 ,  C23F1/00

    CPC分类号： H01L21/31116

    摘要： Method for etching an oxide film in a plasma etching system, specifically in a high concentration plasma etching system, is disclosed, in which a mixture of new etching gas chemistry of first, second and third gases is used in forming an oxide film suitable to an integrated circuit with a high device packing density, for improving an etch rate and an etch selectivity of the oxide film to a sub-layer, the mixture gas consisting of CHF.sub.X /C.sub.a HF.sub.b /C.sub.Y F.sub.Z, CHF.sub.X /CH.sub.b F/C.sub.Y F.sub.Z or CHF.sub.X /CH.sub.a F.sub.b /C.sub.Y F.sub.Z.

    摘要翻译： 公开了一种在等离子体蚀刻系统中蚀刻氧化膜的方法，特别是在高浓度等离子体蚀刻系统中，其中使用第一，第二和第三气体的新的蚀刻气体化学物质的混合物来形成适合于 具有高器件封装密度的集成电路，用于提高氧化膜对子层的蚀刻速率和蚀刻选择性，由CHFX / CaHFb / CYFZ，CHFX / CHbF / CYFZ或CHFX / CHaFb / CYFZ组成的混合气体 。