公开(公告)号：US06784532B2

公开(公告)日：2004-08-31

申请号：US10209847

申请日：2002-07-31

申请人： Dong Zhong ,  Farzaneh Yahyaei-Moayyed ,  David G. Figueroa ,  Chris Baldwin ,  Jiangqi He ,  Yuan-Liang Li

发明人： Dong Zhong ,  Farzaneh Yahyaei-Moayyed ,  David G. Figueroa ,  Chris Baldwin ,  Jiangqi He ,  Yuan-Liang Li

IPC分类号： H01L2352

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

公开(公告)号：US07352557B2

公开(公告)日：2008-04-01

申请号：US11082341

申请日：2005-03-17

申请人： Hyunjun Kim ,  Jiangqi He ,  Joong-Ho Kim ,  Dong-Ho Han

发明人： Hyunjun Kim ,  Jiangqi He ,  Joong-Ho Kim ,  Dong-Ho Han

IPC分类号： H01G4/06

CPC分类号： H01G4/228 ,  H01G2/06 ,  H01G4/30 ,  H01G4/40 ,  Y10T29/435

摘要： An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

摘要翻译： 一种装置和系统及其制造方法可以包括由电介质层分开的多个垂直取向的板，其中垂直定向的板包括联接到板的底侧的多个端子。

公开(公告)号：US20080003717A1

公开(公告)日：2008-01-03

申请号：US11427917

申请日：2006-06-30

申请人： Qing A. Zhou ,  Daoqiang Lu ,  Wei Shi ,  Jiangqi He

发明人： Qing A. Zhou ,  Daoqiang Lu ,  Wei Shi ,  Jiangqi He

IPC分类号： H01L21/00

CPC分类号： H01L24/81 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/731 ,  H01L2224/73207 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.

摘要翻译： 具有堆叠在基板上并且使用两种或更多种不同连接技术电耦合的两个或多个骰子的集成电路（“IC”）封装可以改善高速输入/输出（“I / O”）带宽。 在一个实施例中，一个管芯是处理器，并且至少一个其它管芯是动态随机存取存储器（“DRAM”）。 一个或多个骰子可以变薄并且放置在基底和可以水平偏移的另一个骰子中的一个或多个的一部分之间。 一个或多个骰子可以嵌入在基底中。 骰子可以使用控制崩溃芯片连接（“C4”）和引线键合连接技术的组合彼此耦合到基板。 还描述了制造方法以及将包装应用于电子组件和电子系统。

公开(公告)号：US20070297713A1

公开(公告)日：2007-12-27

申请号：US11452820

申请日：2006-06-13

申请人： Daoqiang Lu ,  Jiamiao Tang ,  Jiangqi He ,  Edward A. Zarbock

发明人： Daoqiang Lu ,  Jiamiao Tang ,  Jiangqi He ,  Edward A. Zarbock

IPC分类号： G02B6/12

CPC分类号： G02B6/4232 ,  G02B6/421 ,  G02B6/4214 ,  G02B6/4246

摘要： A chip-to-chip optical interconnect includes a substrate, an optoelectronic die, and a waveguide structure. The substrate includes an optical via passing through the substrate. The optoelectronic die is disposed on the substrate and aligned to optically communicate through the optical via. A waveguide structure is positioned proximate to the substrate and aligned with the optical via to communicate optical signals with the optoelectronic die through the optical via.

摘要翻译： 芯片到芯片的光学互连包括衬底，光电管芯和波导结构。 衬底包括穿过衬底的光学通孔。 光电管芯设置在衬底上并对准以通过光通孔光学连通。 波导结构被定位在靠近基板并与光通孔对齐以通过光通孔与光电管芯通信光信号。

公开(公告)号：US20070188262A1

公开(公告)日：2007-08-16

申请号：US11709972

申请日：2007-02-22

申请人： Hyunjun Kim ,  Joong-Ho Kim ,  Dong-Ho Han ,  Jiangqi He

发明人： Hyunjun Kim ,  Joong-Ho Kim ,  Dong-Ho Han ,  Jiangqi He

IPC分类号： H01P5/02

CPC分类号： H01P3/081 ,  H01P3/08 ,  H01P5/02

摘要： Transmission line impedance matching for matching an impedance discontinuity on a transmission signal trace with one or more non-transmission traces disposed near the transmission signal trace at a region corresponding to the impedance discontinuity.

公开(公告)号：US20070158807A1

公开(公告)日：2007-07-12

申请号：US11322297

申请日：2005-12-29

申请人： Daoqiang Lu ,  Wei Shi ,  Qing Zhou ,  Jiangqi He

发明人： Daoqiang Lu ,  Wei Shi ,  Qing Zhou ,  Jiangqi He

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00014

摘要： Electronic devices and methods for fabricating electronic devices are described. One embodiment includes an electronic device having a first die, the first die having a top surface, a bottom surface, and a plurality of side surfaces. The first die also includes a plurality of metal pads on the top surface extending to an outer edge of the top surface, and a plurality of metal pads on the bottom surface extending to an outer edge of the bottom surface. The first die also includes a plurality of metal regions along the side surfaces, wherein each of the metal regions extends between one of the metal pads on the top surface and one of the metal pads on the bottom surface. Other embodiments are described and claimed.

摘要翻译： 描述了用于制造电子设备的电子设备和方法。 一个实施例包括具有第一管芯的电子器件，第一管芯具有顶表面，底表面和多个侧表面。 第一管芯还包括在顶表面上延伸到顶表面的外边缘的多个金属焊盘，以及在底表面上延伸到底表面的外边缘的多个金属焊盘。 第一管芯还包括沿着侧表面的多个金属区域，其中每个金属区域在顶表面上的金属焊盘之一和底表面上的金属焊盘中的一个之间延伸。 描述和要求保护其他实施例。

公开(公告)号：US07205638B2

公开(公告)日：2007-04-17

申请号：US10931497

申请日：2004-08-31

申请人： David Gregory Figueroa ,  Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Cengiz Ahmet Palanduz

发明人： David Gregory Figueroa ,  Dong Zhong ,  Yuan-Liang Li ,  Jiangqi He ,  Cengiz Ahmet Palanduz

IPC分类号： H01L29/40

CPC分类号： H01L23/49827 ,  H01L23/481 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/3011 ,  H01L2224/0401

摘要： An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.

摘要翻译： 公开了一种改进的硅结构单元。 在一个实施例中，硅结构块具有通过其的至少两个通孔。 硅结构单元被掺杂，并且通孔填充有第一材料，并且可选地，填充了选定的通孔，而不是用第二材料填充。 在替代实施例中，硅积层的区域具有沉积在其上的金属。

公开(公告)号：US07173803B2

公开(公告)日：2007-02-06

申请号：US10837814

申请日：2004-05-03

申请人： Dong Zhong ,  Jiangqi He ,  Yuan-Liang Li

发明人： Dong Zhong ,  Jiangqi He ,  Yuan-Liang Li

IPC分类号： H01G4/005

CPC分类号： H01G4/232 ,  H01G4/30 ,  H01L23/32 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/00

摘要： An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.

摘要翻译： 在用于微电子器件的电源插座中可以使用数字间电容器。 在一个实施例中，公开了集成的低电阻功率和接地端子配置。 电容器板可选地耦合到电源和接地端子。 公开了两种极性类型。 还描述了一种操作方法。

公开(公告)号：US07142073B2

公开(公告)日：2006-11-28

申请号：US10880637

申请日：2004-06-29

申请人： Hyunjun Kim ,  Joong-Ho Kim ,  Dong-Ho Han ,  Jiangqi He

发明人： Hyunjun Kim ,  Joong-Ho Kim ,  Dong-Ho Han ,  Jiangqi He

IPC分类号： H03H7/38

CPC分类号： H01P3/081 ,  H01P3/08 ,  H01P5/02

摘要： Transmission line impedance matching is described for matching an impedance discontinuity on a transmission signal trace. The apparatus includes a transmission signal trace and a non-transmission trace. The transmission signal trace has an impedance discontinuity, a first length, and a predetermined first width. The non-transmission trace is disposed near the transmission signal trace at a region corresponding to the impedance discontinuity. The non-transmission trace has a second length that is substantially less than the first length of the transmission signal trace. Additionally, the non-transmission trace is configured to be electromagnetically coupled to the transmission signal trace in the presence of a current on the transmission signal trace to provide a matched impedance on the transmission signal trace.

摘要翻译： 描述传输线阻抗匹配以匹配传输信号迹线上的阻抗不连续性。 该装置包括发送信号跟踪和非传输迹线。 发送信号迹线具有阻抗不连续性，第一长度和预定的第一宽度。 在与阻抗不连续性对应的区域处，将非传输迹线布置在发射信号迹线附近。 非透射迹线具有基本上小于发射信号迹线的第一长度的第二长度。 此外，非传输轨迹被配置为在存在传输信号迹线上的电流的情况下电磁耦合到传输信号迹线，以在传输信号迹线上提供匹配的阻抗。

公开(公告)号：US20060261465A1

公开(公告)日：2006-11-23

申请号：US11459951

申请日：2006-07-26

申请人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

发明人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

IPC分类号： H01L23/12

CPC分类号： H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。