公开(公告)号：US20180158493A1

公开(公告)日：2018-06-07

申请号：US15651084

申请日：2017-07-17

申请人： SK hynix Inc.

发明人： Tae-Kyu RYU

IPC分类号： G11C7/10 ,  G11C11/56 ,  G06F3/06 ,  G06F11/08 ,  G11C7/14 ,  G11C29/42 ,  G11C29/50 ,  G11C29/02 ,  G11C16/26

CPC分类号： G11C7/1006 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/08 ,  G06F11/1048 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/5634

摘要： An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the RR table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.

公开(公告)号：US20180151202A1

公开(公告)日：2018-05-31

申请号：US15880913

申请日：2018-01-26

申请人： Maxlinear, Inc.

发明人： Curtis Ling ,  Vadim Smolyakov ,  Timothy Gallagher ,  Glenn Gulak

IPC分类号： G11C5/14 ,  G11C29/02 ,  G11C29/04

CPC分类号： G11C5/144 ,  G06F11/1048 ,  G11C5/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

摘要： A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

公开(公告)号：US09983916B2

公开(公告)日：2018-05-29

申请号：US15179347

申请日：2016-06-10

申请人： SK hynix Inc.

发明人： Kwang-Su Kim ,  Jong-Min Lee

IPC分类号： G06F11/07 ,  G06F11/10 ,  G11C29/50 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

CPC分类号： G06F11/076 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0409

摘要： An operating method of a memory system including a plurality of memory blocks may include grouping the pages of a selected memory block among the plurality of memory blocks based on a program time, sequentially performing a test read on the groups of the pages, detecting an error in the pages of the test-read groups, and reprogramming a page selected based on a result of the error detection.

公开(公告)号：US09972369B2

公开(公告)日：2018-05-15

申请号：US14923345

申请日：2015-10-26

申请人： Rambus Inc.

发明人： Christopher Haywood ,  David Wang

IPC分类号： G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C7/10 ,  G06F11/07 ,  G11C29/04 ,  G11C5/04

CPC分类号： G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C5/04 ,  G11C7/1006 ,  G11C29/52 ,  G11C2029/0411

摘要： A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20180129557A1

公开(公告)日：2018-05-10

申请号：US15469384

申请日：2017-03-24

申请人： Western Digital Technologies, Inc.

发明人： Luiz M. Franca-Neto

IPC分类号： G06F11/10

CPC分类号： G06F11/1048

摘要： Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM, and error correction vector (ECV) information associated with the NVM is stored in an error tracking table (ETT) within one of a dynamic random access memory (DRAM) or a second NVM component. The ETT is then filtered with a Bloom filter to predict a subset of ETT entries that include a reporting of an error in the NVM. A parallel query of the NVM and the ETT is then performed, which includes a query of the NVM that yields a readout of the NVM, and a query of the ETT that is limited to a query of the subset of ETT entries predicted by the Bloom filter which yields a construction of an ECV corresponding to the readout of the NVM.

公开(公告)号：US20180129554A1

公开(公告)日：2018-05-10

申请号：US15343308

申请日：2016-11-04

申请人： International Business Machines Corporation

发明人： Stephen P. Glancy ,  Frank LaPietra ,  Kevin M. Mcilvain ,  Jeremy R. Neaton ,  Richard D. Wheeler

IPC分类号： G06F11/10

CPC分类号： G06F11/102 ,  G06F11/1048 ,  G06F11/1056 ,  G06F12/00 ,  G11C29/76 ,  G11C2029/0411

摘要： An aspect includes providing communication links from a memory controller to contents of a plurality of bit locations in a plurality of memory devices. A failing bit location in the plurality of bit locations is detected by the memory controller. A replacement bit location for the failing bit location is selected and a replacement communication link to the replacement bit location is provided by the memory controller. A request to access contents of the failing bit location received after the selecting and providing the replacement communication link is performed by accessing contents of the replacement bit location via the replacement communication link.

公开(公告)号：US20180129434A1

公开(公告)日：2018-05-10

申请号：US15428745

申请日：2017-02-09

申请人： Western Digital Technologies, Inc.

发明人： Luiz M. Franca-Neto ,  Robert Eugeniu Mateescu

IPC分类号： G06F3/06 ,  G11C15/04 ,  G06F11/08

CPC分类号： G06F3/0619 ,  G06F3/0629 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1048 ,  G11C11/005 ,  G11C15/046

摘要： Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.

公开(公告)号：US09966146B2

公开(公告)日：2018-05-08

申请号：US14636321

申请日：2015-03-03

申请人： Toshiba Memory Corporation

发明人： Daiki Watanabe ,  Hiroshi Sukegawa ,  Hiroshi Yao ,  Tokumasa Hara ,  Naomi Takeda

IPC分类号： G11C29/00 ,  G11C16/26 ,  G11C29/52 ,  G11C11/56 ,  G06F11/10 ,  G11C8/12 ,  G11C29/04

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C8/12 ,  G11C11/5642 ,  G11C29/52 ,  G11C2029/0411

摘要： According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.

公开(公告)号：US20180121361A1

公开(公告)日：2018-05-03

申请号：US15855907

申请日：2017-12-27

申请人： SPIN TRANSFER TECHNOLOGIES, INC.

发明人： Neal BERGER ,  Benjamin Louie ,  Mourad EL-baraji ,  Lester Crudele ,  Daniel Hillman

IPC分类号： G06F12/0862 ,  G06F12/0891

CPC分类号： G06F12/0862 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0855 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/202 ,  G11C5/143 ,  G11C7/1039 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1693 ,  G11C11/1697 ,  G11C29/52 ,  G11C29/74 ,  G11C29/76 ,  G11C2029/4402

摘要： A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

公开(公告)号：US09952781B2

公开(公告)日：2018-04-24

申请号：US14531891

申请日：2014-11-03

申请人： SanDisk Technologies LLC

发明人： Evan Orme ,  James G. Peterson

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F11/10 ,  G11C16/16 ,  G11C29/52 ,  G11C29/04

CPC分类号： G06F11/1044 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1072 ,  G06F12/0238 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/7205 ,  G11C16/16 ,  G11C29/52 ,  G11C2029/0409

摘要： A storage controller identifies a storage location within a storage division that corresponds to a high error rate. In response, the storage controller may refresh data stored on the storage division by relocating data from the storage division and/or initializing (e.g., erasing) the storage division. In some embodiments, the storage division is selectively refreshed by relocating data from the storage location(s) having high error rates, while deferring a full relocation of other data from the storage division. The storage division may be selectively refreshed based on reliability characteristics of the storage division, such as the remaining data retention time calculated for the storage division.