公开(公告)号：US09563369B2

公开(公告)日：2017-02-07

申请号：US14252673

申请日：2014-04-14

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Nhon Toai Quach ,  Susan Carrie ,  Jeffrey Andrews ,  John Sell ,  Kevin Po

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0613 ,  G06F3/0631 ,  G06F3/0674 ,  G06F13/1605 ,  G06F13/1626 ,  G06F13/1642 ,  G06F13/1668

Abstract: Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.

Abstract translation: 提供了应用细粒度的QoS逻辑的系统和方法。 该系统可以包括存储器控制器，该存储器控制器经配置以经由总线结构从多个主器件接收存储器访问请求。 存储器控制器确定多个主器件中的每一个的优先等级，并进一步确定存储器数据总线上每个主器件消耗的存储器数据总线带宽的量。 基于分配给每个主器件的优先级等级和每个主器件消耗的存储器数据总线带宽的数量，存储器控制器应用细粒度的QoS逻辑来计算存储器请求的调度。 基于该时间表，存储器控制器将存储器请求转换为存储器命令，通过存储器命令总线将存储器命令发送到存储器设备，并且经由存储器数据总线从存储器设备接收响应。

公开(公告)号：US20170004097A1

公开(公告)日：2017-01-05

申请号：US15265057

申请日：2016-09-14

Applicant: Atmel Corporation

Inventor： Franck Lunadier ,  Vincent Debout

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/1642 ,  G06F13/14 ,  G06F13/36 ,  G06F13/364 ,  G06F13/4282

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract translation: 公开了一种总线架构，其提供在使用总线通信的模块上的事务队列重新分配。 模块可以通过数字电子电路（例如，硬件或软件或两者的组合）来实现事务请求队列。 通过组合使用事务请求重播机制的乱序系统总线协议，可以避免影响常规系统的一些总线堵塞问题。 模块可以从交易请求队列中排除较不紧急的事务，以便插入更紧急事务的空间。 主事件模块可以在事务处于待处理状态时动态更新事务的服务质量（QoS）值。

公开(公告)号：US09535627B2

公开(公告)日：2017-01-03

申请号：US14044454

申请日：2013-10-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/068 ,  G06F13/1642 ,  G06F13/1668 ,  Y02D10/14

Abstract: A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority.

Abstract translation: 提供了一种用于访问异构存储器系统的系统，方法和计算机可读存储设备。 存储器控制器基于与命令相关联的访问优先级来调度对一组存储器区域中的存储器区域的访问，并且其中该组存储器区域具有相应的访问延迟。 存储器控制器还使用至少两个队列和访问优先级来延迟对该组存储器区域的访问。

公开(公告)号：US20160371203A1

公开(公告)日：2016-12-22

申请号：US14746245

申请日：2015-06-22

Applicant: QUALCOMM TECHNOLOGIES International, Ltd.

Inventor： Klaus Riess ,  Victor Szeto ,  Gary Hum

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1642 ,  G06F13/385 ,  G06F13/4282

Abstract: A system and method communicates with one of two or more secure digital input output (SDIO) units that only one SDIO unit responds when it is being addressed. The SDIO unit has an SDIO clock input port, an SDIO data bus output port, and an SDIO bidirectional command port. Each SDIO unit has an address indicator within it associated with each SDIO unit. An SDIO unit will not respond to an SDIO command unless an SDIO unit address encoded in the SDIO command matches its address indicator. In some configurations, a single multiple SDIO (MSDIO) command may cause two or more SDIO units to return data to a host.

Abstract translation: 一个系统和方法与两个或更多安全数字输入输出（SDIO）单元之一通信，只有一个SDIO单元在被寻址时才响应。 SDIO单元具有SDIO时钟输入端口，SDIO数据总线输出端口和SDIO双向命令端口。 每个SDIO单元都具有与每个SDIO单元相关联的地址指示器。 SDIO单元不会响应SDIO命令，除非SDIO命令中编码的SDIO单元地址与其地址指示符相匹配。 在某些配置中，单个多重SDIO（MSDIO）命令可能会导致两个或多个SDIO单元将数据返回到主机。

公开(公告)号：US20160350030A1

公开(公告)日：2016-12-01

申请号：US15163330

申请日：2016-05-24

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhijing WU

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673 ,  G06F13/1642

Abstract: Embodiments of the present invention disclose an access request scheduling method and apparatus. The method includes: receiving a to-be-enqueued access request, and determining a memory that the to-be-enqueued access request requests to access; writing the to-be-enqueued access request to one queue in one access queue group corresponding to the memory; selecting one candidate access queue from each candidate access queue group, as a to-be-scheduled queue; selecting, from the to-be-scheduled queues according to an access timeslot of each memory, alternative queues that can participate in scheduling in a current clock period; selecting, from the alternative queues, a specified queue in scheduling in the current clock period; extracting a to-be-scheduled access request from the specified queue; and granting an access authorization to the to-be-scheduled access request.

Abstract translation: 本发明的实施例公开了一种访问请求调度方法和装置。 该方法包括：接收待入队列的访问请求，以及确定要被入队的访问请求请求访问的存储器; 将所述入站访问请求写入与所述存储器对应的一个访问队列组中的一个队列; 从每个候选访问队列组中选择一个候选访问队列作为待计划的队列; 根据每个存储器的访问时隙从待排队列中选择可以参与当前时钟周期调度的备用队列; 从当前时钟周期中，从备用队列中选择调度中的指定队列; 从指定的队列提取待调度的访问请求; 以及授予访问授权给待调度的访问请求。

公开(公告)号：US20160342391A1

公开(公告)日：2016-11-24

申请号：US14717716

申请日：2015-05-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Roger G. Hathorn ,  Bret W. Holley ,  Matthew J. Kalos

IPC: G06F5/12 ,  G06F13/12

CPC classification number: G06F13/126 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/067 ,  G06F5/12 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/36 ,  G06F13/4027 ,  G06F2003/0691 ,  G06F2205/126 ,  G06F2213/0008 ,  H04L47/39

Abstract: A control unit monitors a number of transfer ready operations and a number of retry operations during a monitoring period during communication with a plurality of channels. Based, on the monitoring, a number of buffer credits for communication with the plurality of channels is adjusted.

Abstract translation: 控制单元在与多个通道通信期间的监视期间监视多个传送就绪操作和多次重试操作。 基于监视，调整用于与多个信道通信的多个缓冲器信用。

公开(公告)号：US09483502B2

公开(公告)日：2016-11-01

申请号：US13918108

申请日：2013-06-14

Applicant: FUJITSU LIMITED

Inventor： Koichi Onodera ,  Shuji Yamamura ,  Toru Hikichi

IPC: G06F17/30 ,  G06F13/00 ,  G06F13/16

CPC classification number: G06F17/30289 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1642

Abstract: A computational processing device includes: a computational-processor that outputs access requests to a storage device; a plurality of request-holding-units that respectively hold access requests output by the computational processor according to individual access types, the access types being types of access requests; an arbitration-unit that arbitrates access requests held in the plurality of request holding units; a buffer-unit that includes a plurality of entries that hold data; and a buffer-controller that causes one of the plurality of entries to hold data output by the storage device in response to an access request arbitrated by the arbitration unit, on the basis of a result of comparing, for each access type, a count value that counts, for each access type, the number of entries holding data from among the plurality of entries against a maximum value for the number of entries made to hold data for each access type.

Abstract translation: 计算处理装置包括：计算处理器，其向存储装置输出访问请求; 多个请求保持单元，分别保存由计算处理器根据各个访问类型输出的访问请求，访问类型是访问请求的类型; 仲裁单元，其仲裁保存在所述多个请求保存单元中的访问请求; 包括保存数据的多个条目的缓冲器单元; 以及缓冲器控制器，其使得所述多个条目之一响应于所述仲裁单元仲裁的访问请求，根据对于每个访问类型的比较结果，保存由所述存储装置输出的数据的计数值 其针对每个访问类型计算保持来自所述多个条目中的数据的条目的数量与针对每个访问类型保存数据的条目数量的最大值。

公开(公告)号：US09483422B2

公开(公告)日：2016-11-01

申请号：US14232224

申请日：2012-01-31

Applicant: Ted A. Hadley

Inventor： Ted A. Hadley

IPC: G06F12/00 ,  G06F3/00 ,  G06F13/16 ,  H04L9/32 ,  G06F21/54 ,  G06F21/75 ,  H04L9/08 ,  G06F1/24 ,  G06F21/57 ,  G06F12/14 ,  G06F21/60 ,  G06F21/55 ,  G06F21/72 ,  G06F21/79 ,  G06F21/78 ,  G09C1/00 ,  G06F11/22 ,  G06F21/74 ,  G01R31/317

CPC classification number: G06F13/1642 ,  G01R31/31719 ,  G06F1/24 ,  G06F13/1663 ,  G06F21/54 ,  G06F21/55 ,  G06F21/57 ,  G06F21/575 ,  G06F21/602 ,  G06F21/72 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  G06F21/79 ,  G06F2221/2143 ,  G09C1/00 ,  H04L9/088 ,  H04L9/32 ,  H04L2209/12

Abstract: Embodiments herein relate to accessing a memory region including confidential information. A memory request from a process may be received. The memory request may include a process ID (PID) of the process, a requested memory address, and a requested access type. The memory request may be compared to a permission set associated with a memory region including the confidential information. Access to the memory region by the process may be controlled based on the comparison.

Abstract translation: 本文的实施例涉及访问包括机密信息的存储器区域。 可以接收来自进程的存储器请求。 存储器请求可以包括进程的进程ID（PID），请求的存储器地址和请求的访问类型。 存储器请求可以与与包括机密信息的存储器区域相关联的权限集进行比较。 可以基于比较来控制通过处理对存储器区域的访问。

公开(公告)号：US09465755B2

公开(公告)日：2016-10-11

申请号：US14233321

申请日：2011-12-15

Applicant: Ted A. Hadley

Inventor： Ted A. Hadley

IPC: G06F21/78 ,  G06F13/16 ,  H04L9/32 ,  G06F21/54 ,  G06F21/75 ,  H04L9/08 ,  G06F1/24 ,  G06F21/57 ,  G06F12/14 ,  G06F21/60 ,  G06F21/55 ,  G06F21/72 ,  G06F21/79 ,  G09C1/00 ,  G06F11/22 ,  G06F21/74 ,  G01R31/317

CPC classification number: G06F13/1642 ,  G01R31/31719 ,  G06F1/24 ,  G06F13/1663 ,  G06F21/54 ,  G06F21/55 ,  G06F21/57 ,  G06F21/575 ,  G06F21/602 ,  G06F21/72 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  G06F21/79 ,  G06F2221/2143 ,  G09C1/00 ,  H04L9/088 ,  H04L9/32 ,  H04L2209/12

Abstract: Example embodiments disclosed herein relate to security parameter zeroization. Example embodiments include security parameter zeroization based on a remote security monitor.

Abstract translation: 本文公开的示例实施例涉及安全参数归零。 示例实施例包括基于远程安全监视器的安全参数归零。

公开(公告)号：US09465754B2

公开(公告)日：2016-10-11

申请号：US13930088

申请日：2013-06-28

Applicant: Analog Devices, Inc.

Inventor： Alexander Leonard ,  Shipra Bhal ,  Christopher Mayer

IPC: G06F13/16

CPC classification number: G06F13/1642 ,  G06F13/1673

Abstract: A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.

Abstract translation: 电路可以包括队列，监视器和控制器。 队列可以从多个总线接收并存储多个命令以访问共享的一组寄存器。 监视器可以监视队列中的多个命令，以确定是否需要为多个总线中的一个总线的选定命令保留一段时间。 控制器，如果需要保留的时间段，基于由监视器确定的时间段，可以禁止从除了多个总线之一的总线以外的总线接收命令，可以执行所选择的命令 多个总线，并且可以允许多个总线中的多于一个访问所选择的命令的结果。