公开(公告)号：US20090255719A1

公开(公告)日：2009-10-15

申请号：US12475648

申请日：2009-06-01

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

IPC: H05K1/16 ,  H01G4/12

CPC classification number: H01L21/6835 ,  H01G4/236 ,  H01G4/30 ,  H01L21/568 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

Abstract translation: 布线基板包括嵌入其中的基板芯和陶瓷芯片。 基板芯具有在芯主表面处开口的壳体开口部。 陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。 陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。 在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

公开(公告)号：US07580240B2

公开(公告)日：2009-08-25

申请号：US11603161

申请日：2006-11-22

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama

IPC: H01G4/06 ,  H01G4/228

CPC classification number: H05K1/186 ,  H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00

Abstract: A via array capacitor including a capacitor body having a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total volume of the inner electrode layers and the metal-containing layers included in the via array capacitor is from 45 vol.% to 95 vol.% of a volume of the via array capacitor.

Abstract translation: 一种通孔阵列电容器，包括具有第一主表面和第二主表面的电容器体，并且具有其中电介质层和内电极层交替层叠的结构; 多个通孔导体，其将内部电极层彼此导引并且整体上排列成阵列形式; 和设置在第一主表面和第二主表面中的至少一个上的含金属层，其中包含在通孔阵列电容器中的内部电极层和含金属层的总体积为45体积％ 至95体积％的通孔阵列电容器的体积。

公开(公告)号：US07557440B2

公开(公告)日：2009-07-07

申请号：US11508968

申请日：2006-08-24

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

IPC: H01L23/053

CPC classification number: H01L21/6835 ,  H01G4/236 ,  H01G4/30 ,  H01L21/568 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

Abstract translation: 布线基板包括嵌入其中的基板芯和陶瓷芯片。 基板芯具有在芯主表面处开口的壳体开口部。 陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。 陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。 在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

公开(公告)号：US20080251285A1

公开(公告)日：2008-10-16

申请号：US12100527

申请日：2008-04-10

Applicant: Motohiko Sato ,  Kenji Murakami ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama ,  Kozo Yamazaki

Inventor： Motohiko Sato ,  Kenji Murakami ,  Jun Otsuka ,  Manabu Sato ,  Masahiko Okuyama ,  Kozo Yamazaki

IPC: H01G4/06 ,  H05K1/16

CPC classification number: H05K1/0231 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A capacitor is provided having a tough surface portion which prevents cracking that tends to occur when the capacitor is built-in or surface-mounted on a wiring board. A ceramic sintered body of the capacitor includes a capacitor forming layer portion, a cover layer portion and an interlayer portion. The capacitor forming layer portion has a laminated structure wherein ceramic dielectric layers and inner electrodes connected to a peripheral portion of capacitor via conductors, are alternately laminated. The cover layer portion is exposed at a surface portion of the ceramic body and has a laminated structure wherein ceramic dielectric layers and dummy electrodes not connected to the capacitor via conductors, are alternately laminated.

Abstract translation: 提供一种电容器，其具有坚韧的表面部分，其防止当电容器内置或表面安装在布线板上时容易发生的开裂。 电容器的陶瓷烧结体包括电容器形成层部分，覆盖层部分和中间层部分。 电容器形成层部分具有层叠结构，其中陶瓷电介质层和连接到电容器通孔导体的周边部分的内部电极交替层叠。 覆盖层部分在陶瓷体的表面部分露出，并且具有层叠结构，其中不连接到电容器通孔导体的陶瓷电介质层和虚拟电极交替层叠。

公开(公告)号：US07430107B2

公开(公告)日：2008-09-30

申请号：US11837059

申请日：2007-08-10

Applicant: Hidetaka Fukudome ,  Masashi Nishimura ,  Masaaki Taniguchi ,  Yoshio Kawaguchi

Inventor： Hidetaka Fukudome ,  Masashi Nishimura ,  Masaaki Taniguchi ,  Yoshio Kawaguchi

IPC: H01G4/228

CPC classification number: H05K1/0231 ,  H01G4/2325 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15313 ,  H01L2924/3011 ,  H05K1/185 ,  H05K2201/10712 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.

Abstract translation: 单片电容器包括陶瓷层的层叠体，层叠体具有第一表面和第二表面，至少一对第一和第二内部电极，设置在第一表面上的第一和第二外部电极，设置在第二表面上的第三和第四外部电极 第一通孔导体，其将第一外部电极与第一内部电极和第三外部电极电连接并且包含金属氧化物;以及第二通路导体，其将第二外部电极与第二内部电极电连接， 第四外部电极，其含有金属氧化物，其中，在所述第一和第二导体导体的每一个中，所述第二表面侧的端部的金属氧化物含量高于所述第二和第二导体的中心或末端的金属氧化物含量 第一表面。

公开(公告)号：US20080157274A1

公开(公告)日：2008-07-03

申请号：US11648301

申请日：2006-12-29

Applicant: Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

Inventor： Sriram Dattaguru ,  Larry Binder ,  Cengiz A. Palanduz ,  Chris Jones ,  Dave Bach ,  Kaladhar Radhakrishnan ,  Timothe Litt

IPC: H01L29/00

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/50 ,  H01L23/642 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15787 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In some embodiments, an individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor is presented. In this regard, an apparatus is introduced having a table-shaped ceramic interposer containing conductive traces, a silicon voltage regulator coupled with contacts on a first surface of the ceramic interposer, and an array capacitor coupled with contacts on a second surface of the ceramic interposer. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，呈现包含陶瓷插入件，硅电压调节器和阵列电容器的单独子组件。 在这方面，引入了具有包含导电迹线的台式陶瓷插入器的装置，与陶瓷插入器的第一表面上的触点耦合的硅电压调节器，以及与陶瓷插入器的第二表面上的触点耦合的阵列电容器 。 还公开并要求保护其他实施例。

公开(公告)号：US20080128854A1

公开(公告)日：2008-06-05

申请号：US11634026

申请日：2006-12-04

Applicant: Anne E. Augustine ,  Leigh E. Wojewoda ,  Michael J. Hill

Inventor： Anne E. Augustine ,  Leigh E. Wojewoda ,  Michael J. Hill

IPC: H01L29/00

CPC classification number: H01L23/50 ,  H01G4/30 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10712 ,  H01L2224/0401

Abstract: In some embodiments, an embedded array capacitor with top and bottom exterior surface metallization is presented. In this regard, an integrated circuit package is introduced having a plurality of micro-vias, a plurality of dielectric layers, and an array capacitor with metallization substantially covering an exterior surface coupled with the micro-vias and embedded in the dielectric layers. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，呈现具有顶部和底部外表面金属化的嵌入式阵列电容器。 在这方面，引入了具有多个微通孔，多个电介质层和阵列电容器的集成电路封装，其具有基本上覆盖与微通孔耦合并嵌入电介质层中的外表面的金属化。 还公开并要求保护其他实施例。

公开(公告)号：US20080079147A1

公开(公告)日：2008-04-03

申请号：US11542008

申请日：2006-09-29

Applicant: Michael J. Hill ,  Anne E. Augustine ,  Tolga Memioglu

Inventor： Michael J. Hill ,  Anne E. Augustine ,  Tolga Memioglu

IPC: H01L23/34

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/0401

Abstract: In some embodiments, an embedded array capacitor with side terminals is presented. In this regard, an integrated circuit package is introduced having a plurality of micro-vias, a plurality of dielectric layers, and an array capacitor with side terminals coupled with the micro-vias and embedded in the dielectric layers. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，呈现具有侧面端子的嵌入式阵列电容器。 在这方面，引入了具有多个微通孔，多个电介质层和具有与微通孔耦合并嵌入电介质层中的侧端子的阵列电容器的集成电路封装。 还公开并要求保护其他实施例。

公开(公告)号：US20070281394A1

公开(公告)日：2007-12-06

申请号：US11739798

申请日：2007-04-25

Applicant: Tadahiko Kawabe ,  Masao Kuroda ,  Yasuhiro Sugimoto ,  Hajime Saiki ,  Shinji Yuri ,  Makoto Origuchi

Inventor： Tadahiko Kawabe ,  Masao Kuroda ,  Yasuhiro Sugimoto ,  Hajime Saiki ,  Shinji Yuri ,  Makoto Origuchi

IPC: H01L21/02

CPC classification number: H05K1/185 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed, and a gap between the electronic component and the core board is filled with a part of the lowermost resin insulating layer so as to fix the electronic component to the core board. In an opening portion formation step, a portion of the lowermost resin insulating layer located directly above the gap between the electronic component and the core board is removed so as to form an opening portion exposing a part of a core board main surface side conductor and a component main surface side electrode. In a main surface side connecting conductor formation step, a main surface side connecting conductor is formed in the opening portion so as to connect the core board main surface side conductor to the component main surface side electrode.

Abstract translation: 一种制造布线板的方法，其可以简化制造步骤。 在准备步骤中，制备核心板和电子部件。 在绝缘层形成和定影步骤中，在将电子部件容纳在容纳孔中之后，形成最下层的树脂绝缘层，并且用最下层树脂绝缘层的一部分填充电子部件与芯板之间的间隙 以将电子部件固定到核心板。 在开口部形成工序中，除去位于电子部件与芯板之间的间隙正上方的最下层树脂绝缘层的一部分，以形成露出芯板主面侧导体和 部件主表面侧电极。 在主表面侧连接导体形成步骤中，在开口部分形成主表面侧连接导体，以将芯板主表面侧导体连接到部件主表面侧电极。

公开(公告)号：US20070263364A1

公开(公告)日：2007-11-15

申请号：US11739752

申请日：2007-04-25

Applicant: Tadahiko Kawabe ,  Masao Kuroda ,  Yasuhiro Sugimoto ,  Hajime Saiki ,  Shinji Yuri ,  Makoto Origuchi

Inventor： Tadahiko Kawabe ,  Masao Kuroda ,  Yasuhiro Sugimoto ,  Hajime Saiki ,  Shinji Yuri ,  Makoto Origuchi

IPC: H05K7/00

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A wiring board having an excellent electrical property and reliability or the like. The wiring board includes a core board, a capacitor and a resin filler. The core board includes an accommodation hole therein and a core board main surface side conductor disposed on the core main surface thereof. A capacitor main surface side electrode is disposed on a capacitor main surface of the capacitor. A gap between the capacitor accommodated in the accommodation hole and the core board is filled with the resin filler so that the capacitor is fixed to the core board. Further, the resin filler has a main surface side wiring forming portion on which a main surface side connecting conductor, which is connected to an end portion of a via conductor, is disposed so as to connect the core board main surface side conductor to the capacitor main surface side electrode.

Abstract translation: 具有优异的电性能和可靠性等的布线板。 布线板包括芯板，电容器和树脂填料。 芯板包括容纳孔和设置在其芯主表面上的芯板主表面侧导体。 电容器主面侧电极设置在电容器的电容器主表面上。 容纳在容纳孔中的电容器和芯板之间的间隙填充有树脂填料，使得电容器固定到芯板。 此外，树脂填料具有主表面侧布线形成部分，其上连接有通孔导体的端部的主表面侧连接导体，以将芯板主表面侧导体连接到电容器 主表面侧电极。