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13 条记录 (耗时 0.011 秒)

    Braille encoding method and display system
    3.
    发明授权
    Braille encoding method and display system 失效
    盲文编码方法和显示系统

    公开(公告)号：US4840567A

    公开(公告)日：1989-06-20

    申请号：US26108

    申请日：1987-03-16

    申请人： Timothe Litt

    发明人： Timothe Litt

    IPC分类号： G09B21/00

    CPC分类号： G09B21/003

    摘要： A Braille display system which encodes text and displays that text on a mechanical Braille display using a three-dimensional Braille code. Each symbol of the code has four frames each of which comprises a 4X2 dot-position array. When the text first appears on the Braille display, the system initially presents the top frame of each symbol. The system also includes a frame selection control by which a user can cause each of the remaining three frames of the relevant Braille symbol to appear individually on the Braille display. When each succeeding frame appears, it replaces the preceding frame of the same symbol. Thus, by using the frame selection control, a user can examine all four frames of each symbol at his discretion.

    摘要翻译： 盲文显示系统，其使用三维盲文码对文本进行编码并显示在机械盲文显示器上的文本。 代码的每个符号具有四个帧，每个帧包括4×2点位置阵列。 当文本首次显示在盲文显示屏上时，系统最初显示每个符号的顶部框架。 该系统还包括一个帧选择控制，通过该帧选择控制，用户可以使相关盲文符号的剩余三帧中的每一个单独出现在盲文显示器上。 当每个后续帧出现时，它将替换相同符号的前一帧。 因此，通过使用帧选择控制，用户可以自由地检查每个符号的所有四个帧。

    Method and apparatus for efficiently managing bandwidth of a debug data output port or buffer
    5.
    发明授权
    Method and apparatus for efficiently managing bandwidth of a debug data output port or buffer 有权
    用于有效管理调试数据输出端口或缓冲器的带宽的方法和装置

    公开(公告)号：US06816989B2

    公开(公告)日：2004-11-09

    申请号：US10033230

    申请日：2001-12-28

    申请人： Timothe Litt

    发明人： Timothe Litt

    IPC分类号： G01R3128

    CPC分类号： G06F11/267

    摘要： An output port for an integrated circuit includes a bandwidth manager for assisting in the off-loading of internal state data during debug periods. The bandwidth manager operates to take internal state data at its normal frequency, and outputs at least the most important portions of that data to external logic. During periods when the output port is able to keep up with the internal sources being sampled, the bandwidth manager will cause all of the state data to be transmitted. If the output port becomes saturated, the bandwidth manager will select the most important portions of the internal state data to be transmitted off-chip, and will drop the less important information. The bandwidth manager is configured to operate dynamically based on the ability of the output port to keep up with the data being generated by the internal sources. The bandwidth manager determines the importance of data based on principles underlying the structure of packets, rather than on detailed parsing of packets, and without relying on knowledge of packet semantics.

    摘要翻译： 用于集成电路的输出端口包括带宽管理器，用于在调试周期期间辅助内部状态数据的卸载。 带宽管理器操作以其正常频率获取内部状态数据，并将该数据的至少最重要部分输出到外部逻辑。 在输出端口能跟上被采样的内部源的期间，带宽管理器将导致所有的状态数据被传输。 如果输出端口饱和，则带宽管理器将选择要在芯片外传输的内部状态数据的最重要部分，并将丢弃较不重要的信息。 带宽管理器被配置为基于输出端口跟踪内部源生成的数据的动态动态地进行操作。 带宽管理器基于分组结构的原理确定数据的重要性，而不是依赖于分组的详细解析，而不依赖于分组语义的知识。

    Efficient word recognizer for a logic analyzer
    7.
    发明授权
    Efficient word recognizer for a logic analyzer 失效
    逻辑分析仪的高效字识别器

    公开(公告)号：US07096395B2

    公开(公告)日：2006-08-22

    申请号：US10034227

    申请日：2001-12-28

    申请人： Timothe Litt

    发明人： Timothe Litt

    IPC分类号： G01R31/28

    CPC分类号： G06F11/273 ,  G01R31/3177 ,  G06F11/25

    摘要： A system having multiple on-chip logic analyzers (OCLA), each on-chip logic analyzer includes one or more word recognizers. The word recognizer includes a great deal of flexibility for the user, while being capable of implementation with very few gates. The word recognizer includes a Boolean logic portion in which a plurality of conditions can be dynamically segregated into a mutually exclusive set of groups. The conditions in each group are combined by means of a single Boolean function that is programmable. The resultant term (or product) from each group is combined with those of the other groups by a fixed selection of Boolean functions. The output of the Boolean logic section is provided to a counter/timer.

    摘要翻译： 具有多个片上逻辑分析器（OCLA）的系统，每个片上逻辑分析器包括一个或多个字识别器。 单词识别器对于用户而言具有很大的灵活性，同时能够以非常少的门实现。 字识别器包括布尔逻辑部分，其中多个条件可以动态地分离成相互排列的组集合。 每个组中的条件通过可编程的单个布尔函数进行组合。 通过固定的布尔函数选择将来自每个组的合成项（或产品）与其他组的术语（或产品）组合。 布尔逻辑部分的输出被提供给计数器/定时器。

    Method and apparatus for implementing loop compression in a program counter trace
    8.
    发明授权
    Method and apparatus for implementing loop compression in a program counter trace 有权
    在程序计数器跟踪中实现循环压缩的方法和装置

    公开(公告)号：US06691207B2

    公开(公告)日：2004-02-10

    申请号：US10034506

    申请日：2001-12-28

    申请人： Timothe Litt ,  Richard E. Kessler ,  Thomas Hummel

    发明人： Timothe Litt ,  Richard E. Kessler ,  Thomas Hummel

    IPC分类号： G06F1200

    CPC分类号： G06F11/3636 ,  G06F9/381 ,  G06F11/3648

    摘要： A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, while all subsequent iterations are not stored, thus saving space in memory which would otherwise be consumed. The loop detector comprises a content addressable memory (CAM) which is enabled by a user programmed signal. The CAM may be configured with a programmable mask to determine which bits of the incoming PC data to compare with the CAM entries. The depth of the CAM also is programmable, to permit the CAM to be adjusted to cover the number of instructions in a loop.

    摘要翻译： 公开了一种系统，其中片上逻辑分析器（OCLA）包括环路检测器逻辑，其接收输入的程序计数器（PC）数据并检测何时存在软件循环。 当检测到软件循环时，循环检测器可以被配置为将第一循环存储在存储器中，而所有后续迭代都不被存储，从而节省了否则将被消耗的存储器中的空间。 环路检测器包括由用户编程的信号使能的内容寻址存储器（CAM）。 CAM可以配置有可编程掩码，以确定进入的PC数据的哪些比特与CAM条目进行比较。 CAM的深度也是可编程的，以允许调整CAM以覆盖循环中的指令数。

    Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip
    10.
    发明授权
    Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip 有权

    公开(公告)号：US07051239B2

    公开(公告)日：2006-05-23

    申请号：US10034717

    申请日：2001-12-28

    申请人： Timothe Litt

    发明人： Timothe Litt

    IPC分类号： G06F11/00

    CPC分类号： G01R31/3177 ,  G06F11/25

    摘要： A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.