公开(公告)号：US20020105031A1

公开(公告)日：2002-08-08

申请号：US10062462

申请日：2002-02-05

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L021/76 ,  H01L031/0392

CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

公开(公告)号：US20020096719A1

公开(公告)日：2002-07-25

申请号：US10091664

申请日：2002-03-05

申请人： Lockheed Martin Corporation

发明人： Robert Dockerty ,  Nadim Haddad ,  Michael J. Hurt ,  Frederick T. Brady

IPC分类号： H01L021/00 ,  H01L027/12 ,  C30B001/00 ,  H01L027/01

CPC分类号： G06Q40/02 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78618

摘要： A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region. These diffusions are ohmically connected to the body region via a body contact, and these diffusions are also connected to the source region by a self-aligned salicide.

摘要翻译： 公开了辐射硬化绝缘体上硅晶体管。 电介质层设置在基板上，并且晶体管结构设置在电介质层上。 晶体管结构包括体区，源极区，漏极区和栅极层。 主体区域形成在电介质层的第一表面部分上，源区域形成在与第一表面部分相邻的电介质层的第二表面部分上，漏极区域形成在电介质层的第三表面部分上 与第一表面部分相邻，并且栅极层覆盖在主体区域上，并且可操作地在布置在源极区域和漏极区域之间并与其邻接的体区域的该部分中引入通道。 此外，在源区域的两个边缘上放置多个扩散。 这些扩散通过身体接触欧姆连接到身体区域，并且这些扩散也通过自对准的自对准硅胶与源区连接。

公开(公告)号：US20020093030A1

公开(公告)日：2002-07-18

申请号：US09760970

申请日：2001-01-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

IPC分类号： H01L029/74 ,  H01L031/111 ,  H01L021/84 ,  H01L027/12

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/1027 ,  H01L27/1203

摘要： A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance pnull diffusion region. A silicided pnull polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a nnull implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

摘要翻译： 提出了一种具有平面单元结构的T-RAM阵列，其包括多个T-RAM单元。 通过使用掺杂多晶硅来形成多个T-RAM单元中的每一个以形成自对准扩散区域以产生低接触电阻p +扩散区域。 硅化p +多晶硅导线优选地用于将多个T-RAM单元中的每一个连接到参考电压Vref。 通过将n +注入植入到每两个字线之间的间隙中，在每两个字线之间形成自对准结区。 自对准结区域为现有技术的T-RAM单元提供从8F2的单元大小到小于或等于6F2的单元大小的T-RAM单元尺寸的减小。 优选地，T-RAM阵列构建在半导体硅绝缘体（SOI）晶片上，以减少结电容并提高可扩展性。

公开(公告)号：US20020093017A1

公开(公告)日：2002-07-18

申请号：US09765134

申请日：2001-01-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Paul S. Andry ,  Frank R. Libsch ,  Takatoshi Tsujimura

IPC分类号： H01L029/04 ,  H01L031/036 ,  H01L031/0376 ,  H01L029/76 ,  H01L031/20 ,  H01L031/112 ,  H01L021/00 ,  H01L021/84 ,  H01L027/01 ,  H01L023/62 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/78633 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02672 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757

摘要： The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dpoant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.

摘要翻译： 本发明公开了半导体器件，薄膜晶体管（TFT）和TFT的形成工艺。 根据本发明的半导体器件包括顶栅型薄膜晶体管（TFT），所述顶栅型TFT形成在衬底上，所述顶栅型TFT包括：沉积在所述衬底上的绝缘层; 由金属 - 掺杂剂化合物形成的源电极和漏电极，所述金属 - 掺杂剂化合物沉积在所述绝缘层上; 沉积在所述绝缘层和所述源电极和所述漏电极上的多晶Si（多晶硅）层; 通过所述掺杂剂从所述金属掺杂剂化合物的迁移而在所述金属掺杂化合物和所述多晶硅层之间形成欧姆接触层; 沉积在所述多晶硅层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅电极，其中所述多晶硅层通过金属诱导的横向结晶而结晶。

公开(公告)号：US20020089031A1

公开(公告)日：2002-07-11

申请号：US09755572

申请日：2001-01-08

申请人： Chartered Semiconductor Manufacturing Ltd.

发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

IPC分类号： H01L027/12 ,  H01L021/00 ,  H01L021/84

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

公开(公告)号：US20020084489A1

公开(公告)日：2002-07-04

申请号：US09880124

申请日：2001-06-14

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Fumitoshi Yamamoto

IPC分类号： H01L027/12

CPC分类号： H01L29/6625 ,  H01L29/735

摘要： An npn transistor allowing the potential of each terminal to be easily set and superior in characteristics such as withstand-voltage performance and current amplification factor can be obtained. An n-type buried layer on a p-type substrate, a p-type buried layer on the n-type buried layer, n-type epitaxial layers covering the above layers, terminal regions on the surfaces of the layers, p-type outer-periphery layers encircling the terminal regions, and an encirclement layer encircling the layers are included, and p-type base regions and the p-type outer-periphery layer are continued to the p-type buried layer to separate a collector region from a p-type substrate and the n-type buried layer and the n-type encirclement layer are continued to separate the p-type buried layer, the p-type base region, and the p-type outer-periphery layer from the p-type substrate.

摘要翻译： 可以获得允许每个端子的电位容易设定并且具有诸如耐电压性能和电流放大因子等特性优异的npn晶体管。 p型衬底上的n型掩埋层，n型掩埋层上的p型掩埋层，覆盖上述层的n型外延层，层的表面上的端子区域，p型外部 围绕端子区的周边层和围绕层的包围层，p型基极区域和p型外周层继续到p型埋层，以将集电极区域与p 继续从p型衬底和p型衬底以及n型掩埋层和n型包围层将p型掩埋层，p型基极区域和p型外围层从p型衬底分离 。

公开(公告)号：US20020084460A1

公开(公告)日：2002-07-04

申请号：US10080108

申请日：2002-02-21

申请人： FUJITSU LIMITED

发明人： Hidaki Takizawa ,  Shougo Hayashi ,  Takeshi Kinjo ,  Makoto Tachibanaki ,  Kenji Okamoto

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L021/4763 ,  H01L031/0376 ,  H01L027/12

CPC分类号： G02F1/1345 ,  G02F1/13454 ,  G02F1/136204 ,  G02F2001/136254 ,  H01L27/124 ,  H01L27/1244

摘要： A TFT matrix-type liquid crystal display device is used in laptop personal computers and wall TVs. On a transparent insulating substrate 10 there are formed gate bus lines 14 for commonly connecting the-gates of thin film transistors, drain bus lines 16 for commonly connecting the drains of the thin film transistors, and outside terminals 20 and outside terminals 30 opposed respectively to the ends of the gate bus lines and the drain bus lines 16, opposed respectively to the ends of the gate bus lines and the drain bus lines. Gate connection lines 24 for commonly connecting the gate bus lines 14 and drain connection lines 34 for commonly connecting the drain bus lines are formed in regions inner of the outside terminals 20, 30. The thin film transistor matrix device can be fabricated without occurrence of short circuit defects, with little characteristic change and with high yields.

摘要翻译： TFT矩阵型液晶显示装置用于膝上型个人计算机和壁挂式电视机。 在透明绝缘基板10上形成有用于共同连接薄膜晶体管的栅极的栅极总线14，用于共同连接薄膜晶体管的漏极的漏极总线16以及分别对应于外部端子20和外部端子30的外部端子20。 栅极总线和漏极总线16的端部分别与栅极总线和漏极总线的端部相对。 用于共同连接栅极总线14和用于共同连接漏极总线的漏极连接线34的栅极连接线24形成在外部端子20,30内部的区域中。薄膜晶体管矩阵器件可以制造而不发生短路 电路缺陷，几乎没有特性变化和高产率。

公开(公告)号：US20020072200A1

公开(公告)日：2002-06-13

申请号：US09961613

申请日：2001-09-24

申请人： Harris Corporation

发明人： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC分类号： H01L021/46 ,  H01L021/76 ,  H01L021/30 ,  H01L021/20 ,  H01L021/36 ,  H01L027/01 ,  H01L027/12

CPC分类号： H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

摘要： Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

摘要翻译： 描述了集成电路，半导体器件及其制造方法。 每个实施例在装置晶片中示出了在处理晶片上氧化物结合的扩散的掺杂​​背面层。 扩散层可以源于器件手柄，处理晶片，粘合氧化物或多晶硅或外延硅的附加半导体层。 该方法使用热粘合氧化物或热和沉积氧化物的组合。

公开(公告)号：US20020066901A1

公开(公告)日：2002-06-06

申请号：US09975680

申请日：2001-10-10

发明人： Hideo Yamanaka ,  Hisayoshi Yamoto ,  Yuichi Sato ,  Hajime Yagi

IPC分类号： H01L031/20 ,  H01L029/04 ,  H01L027/12

CPC分类号： G02F1/13454 ,  G02F2202/105 ,  G09B5/04 ,  G09B19/06 ,  G10L21/06

摘要： Each of an electrooptical device and a driving substrate for the electrooptical device includes a first substrate having a display section provided with pixel electrodes and a peripheral-driving-circuit section provided on the periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate A gate section including a gate electrode and a gate-insulating film is formed on one surface of the first substrate, a compound layer having high lattice matching with single-crystal silicon is formed on the surface of the first substrate, and a single-crystal silicon layer is formed on the first substrate including the compound layer and the gate section. The single-crystal silicon layer constitutes a channel region, a source region, and a drain region. In addition, a first bottom-gate thin-film transistor having the gate section is formed below the channel region, the first bottom-gate thin-film transistor constituting at least a part of the peripheral-driving-circuit section.

摘要翻译： 电光装置的电光装置和驱动基板中的每一个包括具有设置有像素电极的显示部的第一基板和设置在显示部的周围的外周驱动电路部，第二基板和光学材料 设置在第一基板和第二基板之间的第一基板的一个表面上形成包括栅极电极和栅极绝缘膜的栅极部分，在单晶硅的表面上形成具有高的单晶硅晶格匹配的化合物层 在包括化合物层和栅极部分的第一衬底上形成第一衬底和单晶硅层。 单晶硅层构成沟道区，源极区和漏极区。 此外，具有栅极部分的第一底栅薄膜晶体管形成在沟道区的下方，第一底栅薄膜晶体管构成外围驱动电路部分的至少一部分。

公开(公告)号：US20020053685A1

公开(公告)日：2002-05-09

申请号：US10025894

申请日：2001-12-26

发明人： Sameer Pendharkar ,  Taylor R. Efland

IPC分类号： H01L027/10 ,  H01L027/01 ,  H01L027/12

CPC分类号： H01L29/7835 ,  H01L21/761 ,  H01L29/1087

摘要： A method of minimizing parasitics in an MOS device caused by the formation of a bipolar transistor within the MOS devices and the device, primarily for a polyphase bridge circuit. For the low side device, a substrate of a first conductivity type is provided having a first buried layer of opposite conductivity type thereon. A second buried layer of the first conductivity type is formed over the first buried layer and a further layer of the first conductivity type is formed over the second buried layer. A sinker extending through the further layer to the first buried layer is formed to isolate the second buried layer and the further layer from the substrate. Formation of an MOS device in the further layer including source, drain and gate regions is completed and the sinker is connected to a source terminal of the device. The second buried layer is formed either by coimplanting a p-type dopant and an n-type dopant with one of the dopant having a higher diffusion rate than the other or by implanting and diffusing one of the two dopants first to form one layer and then implanting and diffusing the other dopant to form the second layer. The preferred dopants are boron as the p-type dopant and antimony as the n-type dopant.

摘要翻译： 一种使MOS器件中的寄生效应最小化的方法，其由MOS器件和器件内的双极晶体管形成，主要用于多相桥式电路。 对于低侧装置，提供具有第一导电类型的衬底，其上具有相反导电类型的第一掩埋层。 第一导电类型的第二掩埋层形成在第一掩埋层上，并且第二导电类型的另一层形成在第二掩埋层上。 形成了延伸穿过另一层到第一掩埋层的沉降片，以将第二掩埋层和另外的层与衬底隔离。 在包括源极，漏极和栅极区域的另外的层中形成MOS器件，并且沉降片连接到器件的源极端子。 第二掩埋层通过将p型掺杂剂和n型掺杂剂与其中一种具有比另一种扩散速率更高的扩散速率的掺杂剂或通过首先注入和扩散两种掺杂剂之一形成一层形成，然后 植入和扩散另一种掺杂剂以形成第二层。 优选的掺杂剂是作为p型掺杂剂的硼和作为n型掺杂剂的锑。