Abstract:
The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.
Abstract:
Provided is an ADC in which a plurality of pixel signals input through a vertical signal line of a solid-state image pickup apparatus are held in advance using some capacitors among a plurality of capacitors within the ADC. A potential of a node is generated by the respective pixel signals held in the capacitors. Thereafter, the potential of the node is changed by changing the voltages of counter electrodes of the capacitors, and the digital values of the pixel signals are generated by comparing the potential of the node with a predetermined potential.
Abstract:
An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nth clock signals having different phases; a latch unit that includes first to nth latch units, each of the first to nth latch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nth clock signals; and a count unit that performs a count operation.
Abstract:
In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vx are compared. A count clock CKcnt1 is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage Vx, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise.
Abstract:
A photoelectric conversion apparatus includes a plurality of pixels provided in a plurality of columns, a plurality of analog-to-digital conversion units each provided for a corresponding one of the plurality of columns, and a correction unit. Each of the plurality of analog-to-digital conversion units is configured to convert a signal of a corresponding one of the plurality of pixels into a digital signal at a resolution corresponding to a magnitude of the signal. The correction unit is configured to correct a difference in the resolution.
Abstract:
An image sensor includes, inter alia: a first and second capacitors arranged serially between an input terminal and a first node, a first comparing unit connecting to a first reference signal and a connecting node of the first and second capacitors, and an output terminal connecting to the first node wherein the first comparing unit provides first or second preliminary ramp signals on the first node, first and second switches arranged between the first comparing unit and the first capacitor to selectively connect the first capacitor to a ground voltage or the input terminal, a third capacitor connecting to the second capacitor in parallel, a third switch selectively connecting the first node to the third capacitor, a first ramp signal output unit generating a first ramp signal with the first preliminary ramp signal provided, and a second ramp signal output unit generating a second ramp signal using the second preliminary ramp signal.
Abstract:
A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.
Abstract:
A correlated double sampling circuit includes a first input terminal receiving a ramp signal having first and second ramp sections, a second input terminal receiving a pixel signal, and a comparing circuit comparing the ramp signal with the pixel signal to generate an output signal, wherein the comparing circuit changes a point in time at which the output signal logically transitions during the first ramp section and the second ramp section in response to an applied dithering enable signal.
Abstract:
In a solid-state image sensing element which includes a pixel array portion in which a plurality of pixels each including a photoelectric converter are arranged two-dimensionally, and readout circuits which read out analog pixel signals from the pixel array portion by column, and in which each of the readout circuits includes an A/D conversion circuit which converts the analog pixel signal from the pixel array portion into a digital pixel signal, and the A/D conversion circuit performs A/D conversion by comparing, by a comparison unit, a signal level of the analog pixel signal from the pixel array portion with a temporally changing reference level, a frequency band characteristic of the comparison unit is switched in accordance with the signal level of the analog pixel signal from the pixel array portion.
Abstract:
A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.