公开(公告)号：US09508846B2

公开(公告)日：2016-11-29

申请号：US14662652

申请日：2015-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino Schillaci ,  Alfonso Patti ,  Paola Maria Ponzio

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7831

Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.

Abstract translation: 垂直型的MOS半导体器件具有：具有第一类导电性的功能层; 栅极结构，其形成在功能层上方并具有介电材料区域和电极区域; 具有第二类导电性的主体孔形成在功能层内，并被表面分离区分离; 源区，其具有第一类导电性并形成在体孔内。 每个栅极结构横向仅在一个相应的主体阱上方延伸，并且不与功能层的表面分离区域重叠。 该装置还可以具有：至少一个屏蔽结构，布置在表面分离区域上方的相邻门结构之间; 和/或具有第二类型导电性的至少一个掺杂控制区域，布置在表面分离区域内，两者都被设置在源极电位。

公开(公告)号：US09508520B2

公开(公告)日：2016-11-29

申请号：US14290583

申请日：2014-05-29

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Giuseppe Patti

IPC: H01J1/304 ,  H01J9/02 ,  H01J21/10

CPC classification number: H01J1/3044 ,  H01J9/025 ,  H01J9/027 ,  H01J21/105

Abstract: An integrated vacuum microelectronic device comprises: a highly doped semiconductor substrate, at least one insulating layer) placed above said doped semiconductor substrate, a vacuum aperture formed within said at least one insulating layer and extending to the highly doped semiconductor substrate, a first metal layer acting as a cathode, a second metal layer placed under said highly doped semiconductor substrate and acting as an anode. The first metal layer is placed adjacent to the upper edge of the vacuum aperture and the vacuum aperture has a width dimension such as the first metal layer remains suspended over the vacuum aperture.

Abstract translation: 集成的真空微电子器件包括：放置在所述掺杂半导体衬底之上的高掺杂半导体衬底，至少一个绝缘层），形成在所述至少一个绝缘层内并延伸到高掺杂半导体衬底的真空孔，第一金属层 充当阴极，位于所述高掺杂半导体衬底下方并用作阳极的第二金属层。 第一金属层被放置成与真空孔的上边缘相邻，并且真空孔具有诸如第一金属层保持悬挂在真空孔上的宽度尺寸。

公开(公告)号：US20160344235A1

公开(公告)日：2016-11-24

申请号：US15226473

申请日：2016-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Ramorini ,  Alessandro Gasparini ,  Alberto Cattani

IPC: H02J15/00 ,  H02M7/04

CPC classification number: H02J15/00 ,  H02M3/1588 ,  H02M7/04 ,  H02M7/217 ,  H02M2001/0009 ,  H02N2/181 ,  Y02B70/1466

Abstract: An energy-scavenging interface includes first and second switches connected in series between an input and reference, and third and fourth switches connected in series between the input and an output. A control circuit closes the first and second switches and opens the third switch for a first time interval to store charge in a storage element. A scaled copy of a peak value of the charging current is obtained. The control circuit then opens the first switch and closes the third and fourth switches to generate an output signal as long as the value in current of the output signal is higher than the value of said scaled copy of the peak value.

Abstract translation: 能量清除界面包括串联连接在输入和参考之间的第一和第二开关以及串联连接在输入和输出之间的第三和第四开关。 控制电路关闭第一和第二开关并打开第一开关第一时间间隔以将电荷存储在存储元件中。 获得充电电流的峰值的缩放副本。 只要输出信号的电流值高于峰值的缩放副本的值，控制电路就打开第一开关并闭合第三和第四开关以产生输出信号。

公开(公告)号：US20160336861A1

公开(公告)日：2016-11-17

申请号：US14949531

申请日：2015-11-23

Applicant: STMicroelectronics S.R.L.

Inventor： Giovanni Gritti

IPC: H02M3/335

CPC classification number: H02M3/33507 ,  H02M3/33523 ,  H02M2001/0009 ,  H02M2001/0016 ,  H02M2001/0022

Abstract: A control circuit controls a switch of a switching current converter receiving an input quantity, with a transformer having a primary winding and a sensor element generating a sensing signal correlated to a current in the primary winding. The control circuit has a comparator stage configured to compare a reference signal with a comparison signal correlated to the sensing signal and generate an opening signal for the switch. The comparator stage has a comparator element and a delay-compensation circuit. The delay-compensation circuit is configured to generate a compensation signal correlated to the input quantity and to a propagation delay with respect to the opening signal. The comparator element generates the opening signal with an advance correlated to the input quantity and to the propagation delay.

Abstract translation: 控制电路通过具有初级绕组的变压器和产生与初级绕组中的电流相关的感测信号的传感器元件来控制接收输入量的开关电流转换器的开关。 控制电路具有比较器级，其被配置为将参考信号与与感测信号相关的比较信号进行比较，并产生开关的开路信号。 比较器级具有比较器元件和延迟补偿电路。 延迟补偿电路被配置为产生与输入量相关的补偿信号和相对于打开信号的传播延迟。 比较器元件产生具有与输入量相关的提前和传播延迟的开启信号。

公开(公告)号：US20160332196A1

公开(公告)日：2016-11-17

申请号：US15220208

申请日：2016-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Ugo Ghisu ,  Sandro Rossi ,  Dario Bianchi

IPC: B06B1/02 ,  H03K17/687

Abstract: A transmission channel transmits high-voltage pulses in a transmission phase and receives echoes of the high-voltage pulses in a receiving phase. The transmission channel includes a buffer with anti-memory circuitry to couple drain conduction terminals of buffer transistors of a high-side of a buffer of the transmission channel to a low-side reference voltage of a low-side of the buffer and couple drain conduction terminals of buffer transistors of the low-side of the buffer to a high-side reference voltage of the high-side of the buffer during the clamping phase.

Abstract translation: 传输通道在传输阶段传输高电压脉冲，并在接收阶段接收高电压脉冲的回波。 传输通道包括具有防存储器电路的缓冲器，用于将传输通道的缓冲器的高侧的缓冲晶体管的漏极导通端子耦合到缓冲器的低侧的低侧参考电压并耦合漏极导通 缓冲器的低侧的缓冲晶体管的端子在钳位阶段期间到缓冲器的高侧的高侧参考电压。

公开(公告)号：US09497464B2

公开(公告)日：2016-11-15

申请号：US13827210

申请日：2013-03-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Subarna Tripathi ,  Emiliano Piccinelli

IPC: H04N7/12 ,  H04N19/107 ,  H04N19/149 ,  H04N19/124 ,  H04N19/152 ,  H04N19/162 ,  H04N19/177 ,  H04N19/40 ,  H04N19/105 ,  H04N19/146 ,  H04N19/169

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/124 ,  H04N19/146 ,  H04N19/149 ,  H04N19/152 ,  H04N19/162 ,  H04N19/169 ,  H04N19/177 ,  H04N19/40

Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

Abstract translation: 独立于GOP的动态比特率控制器系统包括用于接收一个或多个输入参数的用户界面，比特率控制器和编码器。 比特率控制器调节输出比特流的比特率。 比特率控制器包括用于确定比特估计和量化参数的多个比特率模块，以及基于所接收的输入参数和帧速率来计算收敛周期的控制模块。 控制模块基于收敛周期选择比特率模块，并且编码器使用由比特率模块确定的量化参数来生成输出比特流。

公开(公告)号：US20160320425A1

公开(公告)日：2016-11-03

申请号：US14971155

申请日：2015-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Procopio ,  Carlo Valzasina

IPC: G01P15/09 ,  H01L41/27 ,  H01L41/25

CPC classification number: G01P15/09 ,  G01L1/16 ,  G01P15/0922 ,  G01P2015/0817 ,  H01L41/1132 ,  H01L41/25 ,  H01L41/27 ,  H01L41/332

Abstract: The piezoelectric sensor is formed in a semiconductor material chip having a surface defining a plane and integrating a structure for sensing forces acting in the plane. The chip is formed by a substrate defining a cantilever having a first end, constrained to an anchorage portion of the substrate, and a second end, which is free to bend under the action of external forces. The cantilever has first and second longitudinal halves, each carrying a respective strip element of piezoelectric material, which extends parallel to the chip plane.

Abstract translation: 压电传感器形成在具有限定平面的表面并且集成用于感测作用在平面中的力的结构的半导体材料芯片中。 芯片由限定悬臂的基板形成，该悬臂具有被限制到基板的锚定部分的第一端和在外力作用下自由弯曲的第二端。 悬臂具有第一和第二纵向半部，每个具有平行于芯片平面延伸的压电材料的相应带状元件。

公开(公告)号：US20160305780A1

公开(公告)日：2016-10-20

申请号：US15192404

申请日：2016-06-24

Applicant: STMicroelectronics S.r.l.

Inventor： Claudia Comi ,  Alberto Corigliano ,  Leonardo Baldasarre

IPC: G01C19/574 ,  G01P15/125 ,  G01P15/097

CPC classification number: G01C19/574 ,  G01C19/56 ,  G01P15/097 ,  G01P15/125 ,  G01P2015/0831

Abstract: An integrated detection structure has a first inertial mass and a second inertial mass, each of which is elastically anchored to a substrate and has a linear movement along a first horizontal axis, a first detection movement of rotation about a first axis of rotation parallel to a second horizontal axis and a second detection movement of translation along the second horizontal axis; driving electrodes cause linear movement of the inertial masses, in opposite directions of the first horizontal axis; a pair of flexural resonator elements and a pair of torsional resonator elements are elastically coupled to the inertial masses, the torsional resonator elements having a resonant movement of rotation about a second axis of rotation and a third axis of rotation, parallel to one another and to the first axis of rotation.

Abstract translation: 集成的检测结构具有第一惯性质量和第二惯性质量，其中每一个惯性质量块和第二惯性质量块都被弹性锚固到基底上，并且沿第一水平轴线具有直线运动，围绕第一旋转轴线旋转的第一检测运动 第二水平轴和沿着第二水平轴的平移的第二检测运动; 驱动电极引起惯性块在第一水平轴线的相反方向上的线性移动; 一对弯曲谐振器元件和一对扭转谐振器元件弹性耦合到惯性块，扭转谐振元件具有围绕彼此平行的第二旋转轴线和第三旋转轴线的共振旋转运动，并且 第一个旋转轴。

公开(公告)号：US09469109B2

公开(公告)日：2016-10-18

申请号：US14531830

申请日：2014-11-03

Applicant: STMicroelectronics S.r.l.

Inventor： Dino Faralli ,  Laura Maria Castoldi ,  Paolo Ferrari ,  Marta Carminati

IPC: B41J2/14 ,  B41J2/16

CPC classification number: B41J2/1433 ,  B41J2/14129 ,  B41J2/1603 ,  B41J2/162 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1632 ,  B41J2/1642 ,  B41J2/1643

Abstract: Embodiments disclose herein are directed to a microfluidic delivery device that has a predominantly semiconductor structure, such as silicon. In particular, the structure for delivering fluid may be formed from polycrystalline silicon, also called polysilicon, or epitaxial silicon. The microfluidic delivery device that predominantly uses silicon based materials to form the structures that are in contact with the dispensed fluid results in a device that is compatible with a wide set of fluids and applications.

Abstract translation: 本文公开的实施方案涉及具有主要半导体结构（例如硅）的微流体递送装置。 特别地，用于输送流体的结构可以由也称为多晶硅的多晶硅或外延硅形成。 主要使用硅基材料以形成与分配的流体接触的结构的微流体递送装置导致与广泛流体和应用相容的装置。

公开(公告)号：US09464952B2

公开(公告)日：2016-10-11

申请号：US14108951

申请日：2013-12-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alberto Pagani ,  Federico Giovanni Ziglioli ,  Bruno Murari

IPC: G01M5/00 ,  G01B5/30 ,  G01B7/16 ,  G01L1/00 ,  G01N3/00 ,  G01L1/18 ,  H01L27/20

CPC classification number: G01L1/18 ,  H01L27/20

Abstract: The integrated electronic device is for detecting a local parameter related to a force observed in a given direction, within a solid structure. The device includes at least one sensor configured to detect the above-mentioned local parameter at least in the given direction through piezo-resistive effect. At least one damping element, integrated in the device, is arranged within a frame-shaped region that is disposed around the at least one sensor and belongs to a substantially planar region comprising a plane passing through the sensor and perpendicular to the given direction. Such at least one damping element is configured to damp forces acting in the planar region and substantially perpendicular to the given direction.

Abstract translation: 集成电子装置用于在固体结构内检测与在给定方向上观察到的力有关的局部参数。 该装置包括至少一个传感器，其配置成至少在给定方向上通过压阻效应来检测上述局部参数。 集成在装置中的至少一个阻尼元件布置在围绕至少一个传感器设置的框状区域中，并且属于基本上平面的区域，该区域包括通过传感器并垂直于给定方向的平面。 这样的至少一个阻尼元件构造成阻碍作用在平面区域中并基本垂直于给定方向的力。