公开(公告)号：US08891317B2

公开(公告)日：2014-11-18

申请号：US13758536

申请日：2013-02-04

Applicant: STMicroelectronics SA

Inventor： Anis Feki ,  Jean-Christophe Lafont ,  David Turgis

IPC: G11C8/00 ,  G11C7/00 ,  G11C5/06 ,  G11C5/02 ,  G11C11/419 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C7/00 ,  G11C8/00 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16 ,  G11C11/419 ,  G11C13/0069 ,  G11C14/0054

Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.

Abstract translation: 包括适于执行数据写入和读取操作的易失性存储单元的易失性存储器。 存储单元以行和列排列，并且进一步分布在用于每一行的单独存储单元组中。 存储器包括被配置为执行写操作的第一存储单元选择电路和与第一电路不同的第二存储单元选择电路，被配置为执行读操作。 第一电路能够为每一行选择来自一组存储器单元的存储器单元用于写入操作。 第二电路能够为每行选择来自存储器单元组之一的存储单元用于读取操作。

公开(公告)号：US20140335383A1

公开(公告)日：2014-11-13

申请号：US14339743

申请日：2014-07-24

Applicant: STMicroelectronics SA

Inventor： Jochen Langheim

IPC: H01M10/48

CPC classification number: H01M10/48 ,  H01M2/20 ,  H01M2/34 ,  H01M2/348 ,  H01M10/488 ,  H01M2200/00 ,  H01M2220/20

Abstract: A method includes coupling two conducting rods between terminals of a battery cell of a battery having several branches coupled in parallel, each branch having several battery cells coupled in series. A force tending to squeeze the rods against each other is applied, with the rods being held apart from each other using an insulating block. At least one operating state signal of the cell is monitored, and the insulating block is removed based on the monitoring, allowing the rods to come into electrical contact and short-circuit the battery cell.

Abstract translation: 一种方法包括在具有并联耦合的多个分支的电池的电池单体的端子之间耦合两个导电棒，每个分支具有串联耦合的多个电池单元。 施加倾向于彼此挤压杆的力，使用绝缘块将杆彼此分离。 监测电池的至少一个操作状态信号，并且基于监测来去除绝缘块，从而允许电极接触并使电池电池短路。

公开(公告)号：US20140292374A1

公开(公告)日：2014-10-02

申请号：US14225520

申请日：2014-03-26

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Philippe Roche ,  Yvain Thonnart

IPC: H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/0016 ,  H01L27/0928 ,  H01L27/11807 ,  H01L27/1203 ,  H03K19/0013 ,  H03K19/01855 ,  H03K2217/0018

Abstract: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference (“BGPD”) of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Abstract translation: 一种用于控制具有逻辑单元和时钟树单元的IC的方法。 每个逻辑单元分别具有第一和第二FET，分别是pMOS和nMOS。 时钟树单元包括分别为pMOS和nMOS的第三和第四FET。 时钟树单元为逻辑单元提供时钟信号。 pMOS-FET的背栅电位差（“BGPD”）是其源电位减去其背栅电位之间的差异，反之亦然是nMOS-FET。 该方法包括将第一和第二后门电位差（BGPD）应用于逻辑单元的第一和第二FET，以及将第三BGPD应用于第三FET，其中第三BGPD为正并且大于施加的第一BGPD，其被应用 同时或将第四BGEPD应用于第四FET，其中第四BGPD为正并且大于并发应用的第二BGPD。

公开(公告)号：US20140273480A1

公开(公告)日：2014-09-18

申请号：US14218380

申请日：2014-03-18

Applicant: STMICROELECTRONICS SA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bernard PREVITALI ,  Christian ARVET

IPC: H01L21/311

CPC classification number: H01L21/31105 ,  H01L21/02005 ,  H01L21/76254

Abstract: The method for producing a substrate provided with protection of its edges has a first step which is providing a substrate having a semiconductor material base. The substrate has opposite first and second main surfaces connected by a lateral surface. A first layer made from first protective material is then formed so as to coat the substrate. The first protective material is then etched on the lateral surface leaving a pattern of first protective material at least partially covering each of the first and second surfaces, and a second protective layer made from second protective material is then formed on the lateral surface devoid of the first protective material. After formation of the second protective layer, the first protective material is eliminated from the substrate.

Abstract translation: 具有保护边缘的基板的制造方法具有提供具有半导体材料基板的基板的第一工序。 基板具有通过侧表面连接的相对的第一和第二主表面。 然后形成由第一保护材料制成的第一层以涂覆基底。 然后在侧表面上蚀刻第一保护材料，留下至少部分地覆盖第一和第二表面中的每一个的第一保护材料的图案，然后在不具有第二保护材料的侧表面上形成由第二保护材料制成的第二保护层 第一保护材料。 在形成第二保护层之后，将第一保护材料从基板上除去。

公开(公告)号：US08819615B2

公开(公告)日：2014-08-26

申请号：US14028188

申请日：2013-09-16

Applicant: STMicroelectronics SA

Inventor： Julien Le Coz ,  Sylvain Engels ,  Alain Tournier

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F2217/84

Abstract: A first assembly of critical cells is to be monitored. An equivalent capacitance of output cells coupled to the critical path is determined. Logic level inputs of the critical cells for signal propagation are also determined. A second assembly of control logic cells is provided which copies the first assembly in terms of number of cells, type of cells and cell connection such that each of the control cells is a homolog of a corresponding critical cell. Charge cells are provided at the outputs of the control cells having an equivalent capacitance in accordance with the determined capacitance of the output cells. For each control cell, logic levels are asserted in accordance with the determined configuration of the critical path. A signal generator applies a signal the input of the second assembly and a signal receiver is coupled to the output of the second assembly.

Abstract translation: 要监测关键电池的第一组装。 确定耦合到关键路径的输出单元的等效电容。 信号传播的关键单元的逻辑电平输入也被确定。 提供了控制逻辑单元的第二组件，其根据单元的数量，单元的类型和单元连接复制第一组件，使得每个控制单元是相应的关键单元的同源物。 根据所确定的输出单元的电容，在具有等效电容的控制单元的输出处提供充电单元。 对于每个控制单元，根据确定的关键路径的配置来确定逻辑电平。 信号发生器将信号施加到第二组件的输入端，信号接收器耦合到第二组件的输出。

公开(公告)号：US20140210071A1

公开(公告)日：2014-07-31

申请号：US14155007

申请日：2014-01-14

Applicant: Anne Lombardot ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Laurent-Luc Chapelon ,  Pascal Ancey ,  Sandrine Lhostis

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract translation: 集成结构包括支撑至少一个芯片的支撑件和附接到芯片的散热壳体。 壳体是导热的并具有与芯片兼容的热膨胀。 壳体还可以包括填充有相变材料的封闭空腔。

公开(公告)号：US20140132338A1

公开(公告)日：2014-05-15

申请号：US14160369

申请日：2014-01-21

Applicant: STMicroelectronics SA

Inventor： Frédéric Hasbani

IPC: H03K3/012

CPC classification number: H03K19/0016 ,  H03K19/0013 ,  H03K2217/0018

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract translation: 本公开中描述的实施例涉及一种用于为集成系统提供电力的方法，包括以下动作：向系统提供电源，接地和体偏置电压，体偏置电压包括p沟道MOS晶体管的体偏置电压， 大于或低于电源电压，以及n沟道MOS晶体管的体偏置电压低于或大于接地电压，根据系统的处理单元是否由系统提供的电压进行选择 在活动或不活动的时段期间，提供用于偏置处理单元的MOS晶体管的主体的电压，以及为处理单元的MOS晶体管的主体提供所选择的电压。

公开(公告)号：US20140070893A1

公开(公告)日：2014-03-13

申请号：US14024508

申请日：2013-09-11

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Andreia Cathelin ,  Janusz Grzyb ,  Yan Zhao

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  H03B27/00 ,  H03L7/099 ,  H03L7/23

Abstract: A frequency oscillator includes a ring oscillator having N inverters coupled in series, where N is an odd integer equal to three or more. A first filter is coupled between an output node of a first of the inverters and an output line of the frequency oscillator. A second filter is coupled between an output node of a second of the inverters and the output line of the frequency oscillator.

Abstract translation: 频率振荡器包括具有串联耦合的N个反相器的环形振荡器，其中N是等于3或更大的奇整数。 第一滤波器耦合在第一反相器的输出节点和频率振荡器的输出线之间。 第二滤波器耦合在第二反相器的输出节点和频率振荡器的输出线之间。

公开(公告)号：US20140070103A1

公开(公告)日：2014-03-13

申请号：US14024481

申请日：2013-09-11

Applicant: STMicroelectronics SA

Inventor： Hani Sherry ,  Andreia Cathelin ,  Andreas Kaiser ,  Ullrich Pfeiffer ,  Janusz Grzyb ,  Yan Zhao

IPC: G01J5/10

CPC classification number: G01J5/22 ,  G01J5/10 ,  G01J5/20 ,  G01J2005/0077 ,  G01J2005/202 ,  G01N21/3581 ,  H01Q23/00 ,  Y10T29/49018

Abstract: A terahertz imager includes an array of pixel circuits. Each pixel circuit has an antenna and a detector. The detector is coupled to differential output terminals of the antenna. A frequency oscillator is configured to generate a frequency signal on an output line. The output line is coupled to an input terminal of the antenna of at least one of the pixel circuits.

Abstract translation: 太赫兹成像器包括像素电路阵列。 每个像素电路具有天线和检测器。 检测器耦合到天线的差分输出端。 频率振荡器被配置为在输出线上产生频率信号。 输出线耦合到至少一个像素电路的天线的输入端。

公开(公告)号：US20140017858A1

公开(公告)日：2014-01-16

申请号：US13933441

申请日：2013-07-02

Applicant: STMicroelectronics SA ,  Commissariat a l'energie atomique et aux energies alternatives

Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones.

Abstract translation: 集成电路包括晶体管，设置在其下的UTBOX埋入绝缘层，设置在层下面的接地平面，布置在平面下的阱，在晶体管的周围形成并延伸穿过该层并进入阱的第一沟槽 位于阱下的衬底，在晶体管的一侧制成的pn二极管，其包括相反掺杂的第一和第二区，第一区被配置为电连接到晶体管的第一电极，其中第一和第二区是 与所述平面共面的第二沟槽，用于分离所述第一和第二区域的第二沟槽，所述第二沟槽延伸穿过所述层进入所述平面并且直到深度小于所述平面和所述阱之间的界面，以及在所述第二沟槽形成之下的第三区域 区域之间的连接处。