公开(公告)号：US08092258B2

公开(公告)日：2012-01-10

申请号：US12984834

申请日：2011-01-05

Applicant: Yehuda Binder

Inventor： Yehuda Binder

IPC: H01R25/00

CPC classification number: H01R31/005 ,  H01R31/065 ,  H04B3/542 ,  H04B2203/5425 ,  H04B2203/5437 ,  H04B2203/5441 ,  H04B2203/5445 ,  H04B2203/545 ,  H04B2203/5454 ,  H04B2203/5491 ,  H04B2203/5495 ,  H04L12/2856 ,  H04L12/2898 ,  H04N7/102 ,  H04N7/106 ,  H04Q11/04 ,  H04Q2213/13012 ,  H04Q2213/1308 ,  H04Q2213/13196 ,  H04Q2213/13199 ,  H04Q2213/13332 ,  H04Q2213/13389

Abstract: In conjunction with a wiring in a house carrying data network signal, a modular outlet (100) includes a base module (100a) and interface module (100b). The base module connects to the wiring and is attached to the surface of a building. The interface module provides a data unit connection. The interface module is mechanically attached to the base module and electrically connected thereto. The wiring may also carry basic service signal such as telephone, electrical power and cable television (CATV). In such a case, the outlet provides the relevant connectivity either as part of the base module or as part of the interface module. Both proprietary and industry standard interfaces can be used to interconnect the module. Furthermore, a standard computer expansion card (such as PCI, PCMCIA and alike) may be used as interface module.

公开(公告)号：US08081529B2

公开(公告)日：2011-12-20

申请号：US13030785

申请日：2011-02-18

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C7/00

CPC classification number: G11C29/32 ,  G11C29/003 ,  G11C29/40 ,  G11C2029/0409 ,  G11C2029/2602

Abstract: A method and system for high speed testing of memories in a multi-device system, where individual devices of the multi-device system are arranged in a serial interconnected configuration. High speed testing is achieved by first writing test pattern data to the memory banks of each device of the multi-device system, followed by local test read-out and comparison of the data in each device. Each device generates local result data representing the absence or presence of a failed bit position in the device. Serial test circuitry in each device compares the local result data with global result data from a previous device. The test circuitry compresses this result of this comparison and provides it to the next device as an updated global result data. Hence, the updated global result data will represent the local result data of all the previous devices.

公开(公告)号：USRE43025E1

公开(公告)日：2011-12-13

申请号：US12566533

申请日：2009-09-24

Applicant: Cem Basceri ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Gurtej S. Sandhu

IPC: B32B9/00

CPC classification number: H01L21/0228 ,  C23C16/029 ,  C23C16/18 ,  C23C16/405 ,  C23C16/45525 ,  H01L21/02183 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/31683 ,  H01L28/40 ,  H01L28/60 ,  Y10T29/417 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element. A second layer comprising the second chemical element can be formed on the interface layer. The first layer might not substantially contain the second chemical element, the second layer might not substantially contain the first chemical element, or both. An apparatus can include a first layer containing a first chemical element, an interface layer chemisorbed on the first layer, and a second layer containing a second element on the interface layer. The interface layer can contain at least one monolayer of the first chemical element intermixed with a second chemical element different from the first chemical element.

Abstract translation: 界面形成方法包括在第一层上形成含有第一化学元素和化学吸附的第一层，所述界面层含有与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。 包含第二化学元素的第二层可以形成在界面层上。 第一层可能基本上不包含第二化学元素，第二层可能基本上不含有第一化学元素，或两者都不包含。 装置可以包括含有第一化学元素的第一层，在第一层上化学吸附的界面层和在界面层上含有第二元素的第二层。 界面层可以包含与第一化学元素不同的第二化学元素混合的第一化学元素的至少一个单层。

公开(公告)号：US08068382B2

公开(公告)日：2011-11-29

申请号：US12564492

申请日：2009-09-22

Applicant: Hong-Beom Pyeon

Inventor： Hong-Beom Pyeon

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C7/20

Abstract: A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state.

Abstract translation: 一种半导体存储器电路，包括：存储器阵列，所述存储器阵列包括各自连接到相应行单元的多个字线，以及多个位线，每个位线连接到相应的单元格列。 所述半导体存储器电路还包括用于选择所述多个字线内的一组字线的至少一个行解码器; 以及多个驱动电路，用于分别驱动多个位线，并将连接到该组字线的单元设置为预定的逻辑状态。 此外，一种用于预设存储器阵列的至少一部分的方法，所述存储器阵列包括多个字线，每个字线连接到相应行的单元。 该方法包括选择多个字线内的一组字线; 并且将连接到该字线组的存储单元同时设置为预定的逻辑状态。

公开(公告)号：US08064741B2

公开(公告)日：2011-11-22

申请号：US10584853

申请日：2003-12-29

Applicant: Matteo Cherchi ,  Giacomo Gorni

Inventor： Matteo Cherchi ,  Giacomo Gorni

IPC: G02B6/26

CPC classification number: G02B6/14 ,  G02B6/305 ,  G02B2006/12038 ,  G02B2006/12061

Abstract: An optical mode converter has a coupling waveguide and a receiving waveguide. The coupling waveguide has at an input end a first effective refractive index and includes a tapered core of a substantially constant refractive index with a substantially square cross section at the input end, which has a size that tapers down moving away from the input end. The coupling waveguide also has a cladding at least partially surrounding the tapered core. The receiving waveguide has a second effective refractive index at an output end and includes a core of a substantially constant refractive index greater than the refractive index of the tapered core of the coupling waveguide and a cladding at least partially surrounding the core. A side surface of the tapered core of the coupling waveguide is optically in contact, in a coupling portion, with the receiving waveguide so as to allow optical coupling between the coupling waveguide and the receiving waveguide. The refractive index of the tapered core of the coupling waveguide is selected so that the first effective refractive index and the second effective refractive index differ from each other in absolute value less than 30% of the difference between the core refractive index and the effective refractive index of the receiving waveguide.

Abstract translation: 光模式转换器具有耦合波导和接收波导。 耦合波导在输入端处具有第一有效折射率，并且包括基本上恒定的折射率的锥形芯，该输入端在输入端具有基本上正方形的横截面，其具有从输入端向下移动的尺寸。 耦合波导还具有至少部分围绕锥形芯的包层。 接收波导在输出端具有第二有效折射率，并且包括大于连接波导的锥形芯的折射率的基本恒定的折射率的芯和至少部分地围绕芯的包层。 耦合波导的锥形芯的侧表面在耦合部分中与接收波导光学地接触，以允许耦合波导和接收波导之间的光耦合。 选择耦合波导的锥形芯的折射率，使得第一有效折射率和第二有效折射率彼此之间的绝对值小于芯折射率与有效折射率之差的30％ 的接收波导。

公开(公告)号：US20110252206A1

公开(公告)日：2011-10-13

申请号：US13008522

申请日：2011-01-18

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G06F12/02 ,  G11C11/00

CPC classification number: G11C7/1015 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2013/0088

Abstract: A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

Abstract translation: 存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。 每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。 可变数据宽度控制器与存储器通信。 可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。 要编程的每个位处于特定的逻辑状态。 当编程号码超过最大数量时，划分块将字分成两个或多个子字。 开关与分区块通信。 开关依次提供一个或多个写入脉冲。 每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

公开(公告)号：US08000430B2

公开(公告)日：2011-08-16

申请号：US11999162

申请日：2007-12-04

Applicant: Peter Vlasenko ,  Dieter Haerle

Inventor： Peter Vlasenko ,  Dieter Haerle

IPC: H03D3/24

CPC classification number: H03L7/081 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract translation: 延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。 该DLL结合了模拟域和数字域。 数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。 模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

公开(公告)号：US20110194365A1

公开(公告)日：2011-08-11

申请号：US13091465

申请日：2011-04-21

Applicant: Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON

Inventor： Jin-Ki KIM ,  HakJune OH ,  Hong Beom PYEON

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C5/025

Abstract: Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

Abstract translation: 公开了用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接设备包括连接到至少一个分立存储器设备的本地控制接口，连接到至少一个分立存储器设备的本地输入/输出接口以及插入本地控制接口和本地控制接口之间的全局输入/输出接口 输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US07983099B2

公开(公告)日：2011-07-19

申请号：US12258056

申请日：2008-10-24

Applicant: Jin-Ki Kim

Inventor： Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

Abstract: A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

Abstract translation: 兼容异步操作和同步串行操作的双功能存储器件架构。 双功能存储设备架构包括具有两个不同功能分配的一组物理端口。 存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。 信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。 模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。 开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。 适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

公开(公告)号：US20110170367A1

公开(公告)日：2011-07-14

申请号：US13072097

申请日：2011-03-25

Applicant: Jin-Ki KIM ,  HakJune OH

Inventor： Jin-Ki KIM ,  HakJune OH

IPC: G11C11/402

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/40622

Abstract: A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.

Abstract translation: 动态随机存取存储器件包括多个存储器子块。 每个子块具有连接多个数据存储单元的多个字线。 部分阵列自刷新（PASR）配置设置是独立制作的。 根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。 可以选择子块地址的任何种类的组合。 因此，存储器子块被完全独立地刷新。 用于数据保留的用户可选择的存储器阵列提供有效的存储器控​​制编程，特别是对于低功率