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公开(公告)号：US06527856B2
公开(公告)日：2003-03-04
申请号：US09792040
申请日：2001-02-22
IPC分类号： C30B2502
CPC分类号： C30B33/00 , C30B29/22 , C30B29/225 , C30B33/12 , H01L21/02197 , H01L21/02359 , H01L21/31691 , H01L39/2458
摘要： A method for changing the surface termination of a perovskite substrate surface, an example of which is the conversion of B-site terminations of a single-crystal STO substrate to A-site terminations. The method generally comprises the steps of etching the substrate surface by applying a reactive plasma thereto in the presence of fluorine or another halogen, and then annealing the substrate at a temperature sufficient to regenerate a long range order of the surface, i.e., the surface termination contributes to a better long range order in a film epitaxially grown on the surface. More particularly, the resulting substrate surfaces predominantly contains A-site surface terminations, i.e., SrO for STO (100) substrates. As a result, disadvantages associated with B-site terminated perovskite substrate surfaces are avoided. A suitable etching treatment is a low power oxygen ashing in the presence of low halogen levels. A-site terminated surfaces produced by this invention allow for the epitaxial growth of heterostructures, such as cuprate films for use as high-Tc superconductor films, Josephson tunnel junctions, superlattices and OxFET, with improved quality.
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公开(公告)号：US06479847B2
公开(公告)日：2002-11-12
申请号：US09306509
申请日：1999-05-07
IPC分类号： H01L2975
CPC分类号： H01L49/003 , H01L21/8238
摘要： A method of manufacturing an integrated circuit device includes forming a laminated structure having a first side and a second side, the first side includes a first type Mott channel layer and the second side includes a second type Mott channel layer. A first source region and a first drain region is formed on the first side, a second source region and a second drain region is formed on the second side, a first gate region is formed on the second side, opposite the first source region and the first drain region and a second gate region is formed on the first side, opposite the second source region and the second drain region. The first source, the first drain and the first gate comprise a first type field effect transistor and the second source, the second drain and the second gate comprise a second type field effect transistor.
摘要翻译： 一种集成电路器件的制造方法包括：形成具有第一侧面和第二侧面的层叠结构体，第一面包括第一类型的Mott沟道层，第二面包括第二类型的Mott沟道层。 第一源区和第一漏区形成在第一侧上，第二源区和第二漏区形成在第二侧上，第一栅极区形成在与第一源区相对的第二侧上， 第一漏区和第二栅区形成在与第二源区和第二漏区相对的第一侧上。 第一源极，第一漏极和第一栅极包括第一类型场效应晶体管，第二源极，第二漏极和第二栅极包括第二类型场效应晶体管。
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公开(公告)号：US5563583A
公开(公告)日：1996-10-08
申请号：US344805
申请日：1994-11-23
申请人： Michael J. Brady , Praveen Chaudhari , Richard J. Gambino , Harley K. Heinrich , Paul A. Moskowitz , Alejandro G. Schrott , Robert J. von Gutfeld
发明人： Michael J. Brady , Praveen Chaudhari , Richard J. Gambino , Harley K. Heinrich , Paul A. Moskowitz , Alejandro G. Schrott , Robert J. von Gutfeld
IPC分类号： B42D15/10 , G06K7/08 , G06K17/00 , G06K19/02 , G06K19/067 , G08B13/24 , G09F3/00 , G08B13/14
CPC分类号： G08B13/2408 , G06K19/0672 , G08B13/2417 , G08B13/2437 , G08B13/2442 , G08B13/2471
摘要： A radio frequency (RF) multibit tag structure useful for identifying objects of interest is described. An array of thin cantilevers of slightly different lengths produced by differential etching are coated with a soft magnetic material which upon interrogation with an RF magnetic field vibrate at their resonant frequencies in the presence of an appropriate bias or direct current (DC) field. The oscillating magnetic fields generated by the vibrating bars and the stationary DC field can be readily detected by a receiver and processed to determine the code of the tag and thus provide information related to the object.
摘要翻译： 描述了用于识别感兴趣对象的射频（RF）多位标签结构。 通过差分蚀刻产生的稍微不同长度的薄悬臂梁的阵列涂覆有软磁材料，当在适当的偏置或直流（DC）场的存在下，RF振荡器在其谐振频率下进行询问时进行振荡。 由振动棒和固定的DC场产生的振荡磁场可以容易地由接收器检测并被处理以确定标签的代码，从而提供与该对象有关的信息。
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公开(公告)号：US5382447A
公开(公告)日：1995-01-17
申请号：US161764
申请日：1993-12-02
IPC分类号： H01L21/48 , H01L21/768 , H05K3/38 , H05K3/46 , B05D5/12
CPC分类号： H01L21/76886 , H01L21/4857 , H05K3/384 , H05K2201/0154 , H05K2203/0315 , H05K2203/072 , H05K3/385 , H05K3/4644
摘要： The invention provides a multilayer laminar interconnect package comprising a plurality of conductor circuit layers adhering to and sandwiched between a plurality of dielectric polyimide polymer layers where the conductor circuit layers are a circuit pattern of lines of conductive metal. The conductive metal, e.g. copper, is coated with a capping layer of a metal, e.g. cobalt, which capping layer is further characterized as having a thin layer of the capping metal oxide adhered to the surface thereof. The conductive layer is in contact with an overcoated polyimide dielectric layer such that the surface oxidized capping layer forms an adherent barrier layer at the interface of the polyimide and conductive line layers. The invention also provides a process for producing such interconnect packages.
摘要翻译： 本发明提供一种多层层状互连封装，其包括粘附并夹在多个电介质聚酰亚胺聚合物层之间的多个导体电路层，其中导体电路层是导电金属线的电路图案。 导电金属，例如 铜被涂覆有金属覆盖层，例如金属。 钴，该封盖层进一步表征为具有附着在其表面上的封盖金属氧化物的薄层。 导电层与外涂聚酰亚胺电介质层接触，使得表面氧化覆盖层在聚酰亚胺和导电层的界面处形成粘附阻挡层。 本发明还提供了一种用于生产这种互连封装的方法。
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85.发明授权
公开(公告)号：US5260108A
公开(公告)日：1993-11-09
申请号：US849273
申请日：1992-03-10
CPC分类号： C23C18/14 , H01L21/32051 , H05K3/185
摘要： Precise, adherent deposits of a metal such as palladium are formed on an substrate such as polyimide, silicon dioxide, tantalum oxide and polyethylene terephthalate by contacting the substrate surface with a solution of the metal, and then exposing the surface through the solution to laser radiation characterized by a wavelength absorbable by the substrate and a power density and fluence effective to release electrons to promote deposition of the metal onto the substrate without thermal activation of the substrate or the solution.
摘要翻译： 通过使基板表面与金属溶液接触，在诸如聚酰亚胺，二氧化硅，氧化钽和聚对苯二甲酸乙二醇酯的基板上形成金属如钯的精确粘附沉积物，然后将表面通过溶液暴露于激光辐射 其特征在于由衬底吸收的波长和有效释放电子以促进金属沉积到衬底上的功率密度和注量，而不会热激活衬底或溶液。
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公开(公告)号：US08633464B2
公开(公告)日：2014-01-21
申请号：US13350967
申请日：2012-01-16
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译： 一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面 沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面 每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极 。
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公开(公告)号：US08471236B2
公开(公告)日：2013-06-25
申请号：US13550091
申请日：2012-07-16
IPC分类号： H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。
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公开(公告)号：US20130087756A1
公开(公告)日：2013-04-11
申请号：US13268151
申请日：2011-10-07
CPC分类号： H01L45/1246 , H01L45/06 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： A memory cell structure and method to form such structure. An example memory cell includes a bottom electrode formed within a substrate. The memory cell also includes a phase change memory element in contact with the bottom electrode. The memory cell includes a liner laterally surrounding the phase change memory element. The liner includes dielectric material that is thermally conductive and electrically insulating. The memory cell includes an insulating dielectric layer laterally surrounding the liner. The insulating dielectric layer includes material having a lower thermal conductivity than that of the liner.
摘要翻译： 存储单元结构和形成这种结构的方法。 示例性存储单元包括形成在衬底内的底部电极。 存储单元还包括与底部电极接触的相变存储元件。 存储单元包括横向围绕相变存储元件的衬垫。 衬垫包括导热并电绝缘的电介质材料。 存储单元包括横向围绕衬垫的绝缘介电层。 绝缘介电层包括具有比衬里更低导热性的材料。
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公开(公告)号：US08344351B2
公开(公告)日：2013-01-01
申请号：US13159594
申请日：2011-06-14
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A phase change memory device includes a plurality of memory cells comprising a substrate having a contact surface with an array of conductive contacts to be connected with access circuitry and a nitride layer formed at the contact surface. A plurality of vias are formed through the nitride layer to the contact surface and correspond to each conductive contact, the vias including a conformal conductive seed layer lining each via along exposed portions of the nitride layer and the contact surface and having oxidized edges. A dielectric layer is recessed within the conformal conductive seed layer and exposes a center region of each via. A phase change material is recessed within the center region of each via. A conductive material that remains conductive upon oxidation is formed over the phase change material. A top electrode is formed on each memory cell.
摘要翻译： 相变存储器件包括多个存储单元，其包括具有与要与接触电路连接的导电触点阵列的接触表面的衬底和在接触表面形成的氮化物层。 多个通孔通过氮化物层形成到接触表面并且对应于每个导电接触，通孔包括沿着氮化物层和接触表面的暴露部分并且具有氧化边缘的每个通孔衬里的共形导电种子层。 电介质层凹入保形导电晶种层内并露出每个通孔的中心区域。 相变材料凹陷在每个通孔的中心区域内。 在相变材料上形成氧化时保持导电的导电材料。 在每个存储单元上形成顶部电极。
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公开(公告)号：US08283650B2
公开(公告)日：2012-10-09
申请号：US12550048
申请日：2009-08-28
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译： 一种具有平底下电极的相变存储单元及其制造方法。 该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面 导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极 。
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