公开(公告)号：US20160372570A1

公开(公告)日：2016-12-22

申请号：US14902205

申请日：2014-06-13

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xuan Huang ,  Wanli Wang ,  Genyi Wang

IPC: H01L29/66 ,  H01L21/304 ,  H01L29/739 ,  H01L29/08 ,  H01L29/49 ,  H01L23/31 ,  H01L29/10 ,  H01L21/306

CPC classification number: H01L29/66333 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L23/3171 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/7395

Abstract: A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate. The method has no specific requirement with respect to sheet flow capacity, nor requires a double-sided exposure machine apparatus, is compatible with a conventional process, and has a simple process and high efficiency.

Abstract translation: 一种制造IGBT的方法，包括：提供具有第一表面和第二表面以及第一或第二类型电导的基板; 在基板的第一表面上间隔地形成槽; 将第二或第一类电导体的半导体材料填充到沟槽中以形成通道，其中通道的导电类型不同于衬底的电导的类型; 在所述衬底的所述第一表面上接合以形成所述第二类型电导的漂移区域; 基于漂移区域形成IGBT的前侧结构; 从衬底的第二表面开始稀释衬底，直到通道暴露; 以及在通道和薄化的基板上形成后侧金属电极。 该方法对于纸张流动能力没有特别要求，也不需要双面曝光机装置，与常规方法兼容，并且具有简单的工艺和高效率。

公开(公告)号：US09443926B2

公开(公告)日：2016-09-13

申请号：US14901606

申请日：2014-06-06

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo Zhang ,  Qiang Rui ,  Xiaoshe Deng ,  Genyi Wang

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L23/528 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L29/0607 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53219 ,  H01L23/53247 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/7393 ,  H01L29/7395

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract translation: 场阻反向导通绝缘栅双极晶体管及其制造方法。 晶体管包括端子结构（200）和有源区（100）。 场阻反向导通绝缘栅双极晶体管的底层是N型衬垫，衬垫的背面设置有N型电场停止层（1），电场停止层的一个表面 在背衬P型结构（10）的背面设置有背面金属层（12）的背面P型结构（10）的表面。 在有源区（100）中形成有从背面P型结构（10）贯穿电场停止层（1）的多个多晶硅填充结构（11）。

公开(公告)号：US20160240528A1

公开(公告)日：2016-08-18

申请号：US14901622

申请日：2014-06-09

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaoshe DENG ,  Shuo ZHANG ,  Qiang RUI ,  Genyi WANG

IPC: H01L27/07 ,  H01L29/739 ,  H01L29/06 ,  H01L29/868 ,  H01L21/8249

CPC classification number: H01L27/0727 ,  H01L21/8249 ,  H01L29/0619 ,  H01L29/0684 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/868

Abstract: An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1S2) of the semiconductor substrate (1).

Abstract translation: 提供了具有内置二极管的绝缘栅双极转换器（IGBT）及其制造方法。 IGBT包括：具有第一主表面（1S1）和第二主表面（1S2）的第一导电类型的半导体衬底（1），其中半导体衬底（1）包括有源区（100）和端子 保护区域（200），其位于有源区域的外侧; 绝缘栅晶体管单元，其形成在有源区（100）的第一主表面（1S1）侧，其中在其导通期间在其上形成第一导电类型的沟道; 以及形成在半导体衬底（1）的第二主表面（1S2）侧的第一导电类型和第二导电类型的有源区的第二半导体层（11）的第一半导体层（10） 交替地，其中IGBT仅包括端子保护区域（200）中位于半导体衬底（1）的第二主表面（1S2）侧的第二半导体层（11）。

公开(公告)号：US09343454B2

公开(公告)日：2016-05-17

申请号：US14130481

申请日：2013-04-27

Applicant: CSMC Technologies Fab1 Co., Ltd.

Inventor： Yonghai Hu ,  Meng Dai ,  Zhongyu Lin ,  Guangyang Wang

IPC: H01L29/66 ,  H01L21/338 ,  H01L27/02 ,  H01L29/87 ,  H01L21/762 ,  H01L21/8232

CPC classification number: H01L27/0255 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/26513 ,  H01L21/32055 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/8232 ,  H01L27/0248 ,  H01L29/402 ,  H01L29/66121 ,  H01L29/87

Abstract: An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

Abstract translation: 静电放电保护结构包括：第一导电类型的衬底，第二导电类型的阱区，衬底中的衬底接触区域和第一类型的导电性，阱区和第二类型的阱接触区域 在衬底接触区域和阱接触区域之间的导电性，衬底反掺杂区域和第二类型的导电性，衬底接触区域和阱接触区域之间的良好的反掺杂区域以及第一类型的导电性，通信 在衬底和阱区之间的横向结合处的区域，衬底反掺杂区域和连通区域之间的第一隔离区域，阱对掺杂区域和连通区域之间的第二隔离区域， 第一隔离区和衬底上的另一端，以及氧化物层上的场板结构。

公开(公告)号：US09202790B2

公开(公告)日：2015-12-01

申请号：US14411550

申请日：2012-10-22

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zhongyu Lin ,  Meng Dai ,  Yonghai Hu

IPC: H01L27/00 ,  H01L23/60 ,  H01L27/02 ,  H01L29/74 ,  H01L29/06

CPC classification number: H01L23/60 ,  H01L27/0262 ,  H01L29/0692 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.

Abstract translation: 用于静电放电保护的半导体器件包括衬底，形成在衬底中的第一阱和第二阱。 第一和第二阱分别并列形成，在界面处相遇，分别具有第一导电型和第二导电型。 在第一阱中形成第一重掺杂区和第二重掺杂区。 在第二阱中形成第三重掺杂区和第四重掺杂区。 第一，第二，第三和第四重掺杂区域分别具有第一，第二，第二和第一导电类型。 第一和第二重掺杂区域的位置沿平行于界面的方向错开。

公开(公告)号：US20150295069A1

公开(公告)日：2015-10-15

申请号：US14436016

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jian Xu ,  Min He ,  Shu Zhang ,  Zehuang Luo ,  Xiaojia Wu

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/66681 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76213 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/408

Abstract: A manufacturing method for a semiconductor device with a discrete field oxide structure is provided, the method includes: growing a first PAD oxide layer on the surface of a wafer; forming a first silicon nitride layer (302) on the first PAD oxide layer through deposition; defining a field region by photolithography and etching same to remove the first silicon nitride layer (302) located on the field region; performing an ion implantation process to the field region; performing field region oxidation to grow a field oxide layer (304); peeling off the first silicon nitride layer (302); wet-dipping the wafer to remove the first PAD oxide layer and a part of field oxide layer (304); growing a second PAD oxide layer on the surface of the wafer, and forming a second silicon nitride layer (312) on the second PAD oxide layer through deposition; defining a drift region by photolithography and etching same to remove the second silicon nitride layer (312) on the drift region; performing an ion implantation process to the drift region; and performing drift region oxidation to grow a drift region oxide layer (314). The above-mentioned method peels off the silicon nitride layer (302) after the growth of the field oxide layer (304) is finished, at this time, the length of a bird beak of field-oxide (304) can be optimized by adjusting a wet-dipping amount to solve the problem that the bird beak of field-oxide (304) is too long.

Abstract translation: 提供一种具有离散场氧化物结构的半导体器件的制造方法，该方法包括：在晶片表面上生长第一PAD氧化物层; 通过沉积在所述第一PAD氧化物层上形成第一氮化硅层（302）; 通过光刻法定义场区域并进行蚀刻以去除位于场区域上的第一氮化硅层（302）; 对场区进行离子注入工艺; 进行场区氧化以生长场氧化物层（304）; 剥离第一氮化硅层（302）; 湿浸湿晶片以去除第一PAD氧化物层和一部分场氧化物层（304）; 在所述晶片的表面上生长第二PAD氧化物层，并且通过沉积在所述第二PAD氧化物层上形成第二氮化硅层（312）; 通过光刻法定义漂移区域并进行蚀刻以去除漂移区域上的第二氮化硅层（312）; 对漂移区域进行离子注入工艺; 以及进行漂移区氧化以生长漂移区氧化物层（314）。 上述方法在场氧化物层（304）的生长完成之后，剥离氮化硅层（302），此时可以通过调整场氧化物（304）的鸟喙的长度来优化 用于解决场氧化物（304）的鸟喙太长的问题的湿浸量。

公开(公告)号：US20150155182A1

公开(公告)日：2015-06-04

申请号：US14411978

申请日：2013-07-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Qiang Rui ,  Shuo Zhang ,  Genyi Wang ,  Xiaoshe Deng

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01L21/32105 ,  H01L21/32137 ,  H01L29/66325 ,  H01L29/66333

Abstract: Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.

Abstract translation: 公开了一种在具有场停止结构（10）的IGBT的背面上去除多晶硅保护层（12）的方法。 该方法包括在IGBT的背面上热氧化多晶硅保护层（12），直到在位于多晶硅保护层（12）上方的栅极氧化物层（11）上终止氧化以形成二氧化硅层（13） ，并通过干式蚀刻工艺除去形成的二氧化硅层（13）和栅极氧化物层（11）。 去除保护层的方法更容易控制。

公开(公告)号：US09006867B2

公开(公告)日：2015-04-14

申请号：US14364933

申请日：2012-11-20

Applicant: CSMC Technologies FAB1 Co., Ltd.

Inventor： Xinwei Zhang ,  Changfeng Xia ,  Chengjian Fan ,  Wei Su

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L22/30 ,  H01L21/30608 ,  H01L21/3083 ,  H01L22/12

Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and W1 respectively, Wu=du/0.71, and W1=du/0.71, where du is the maximum wet etching depth to be monitored, and d1 is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.

Abstract translation: 提供了硅湿蚀刻​​深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽，其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和W1，Wu = du / 0.71，W1 = du / 0.71，其中du是要监测的最大湿蚀刻深度，d1是湿蚀刻深度的最小值 被监视。 该方法包括：根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻，形成待监测的蚀刻凹槽和用于监测凹槽深度的结构，然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度，并且获得更高的监视精度。

公开(公告)号：US20140346647A1

公开(公告)日：2014-11-27

申请号：US14364933

申请日：2012-11-20

Applicant: CSMC TECHNOLOGIES FAB1 CO.,LTD

Inventor： Xinwei Zhang ,  Changfeng Xia ,  Chengjian Fan ,  Wei Su

IPC: H01L21/66 ,  H01L21/308

CPC classification number: H01L22/30 ,  H01L21/30608 ,  H01L21/3083 ,  H01L22/12

Abstract: A monitoring structure and a relevant monitoring method for the silicon wet etching depth are provided. The structure includes a wet etched groove formed on a monocrystalline silicon material with at least two top surfaces thereof being rectangular; and the top surface widths of the grooves are Wu and Wl respectively, Wu=du/0.71, and Wl=du/0.71, where du is the maximum wet etching depth to be monitored, and dl is the minimum of the wet etching depth to be monitored. The method includes: performing anisotropic wet etching on a monocrystalline silicon wafer according to a pattern with a monitoring pattern, forming an etched groove to be monitored and a structure for monitoring the depth of the groove, and then monitoring the structure to monitor the wet etching depth. The etching depth of the groove can be monitored with low costs, and a higher monitoring accuracy is obtained.

Abstract translation: 提供了硅湿蚀刻​​深度的监测结构和相关监测方法。 该结构包括形成在单晶硅材料上的湿蚀刻槽，其至少两个顶表面是矩形; 并且槽的顶面宽度分别为Wu和Wl，Wu = du / 0.71，Wl = du / 0.71，其中du是要监测的最大湿蚀刻深度，d1是湿蚀刻深度的最小值 被监视。 该方法包括：根据具有监测图案的图案在单晶硅晶片上进行各向异性湿蚀刻，形成待监测的蚀刻凹槽和用于监测凹槽深度的结构，然后监测结构以监测湿蚀刻 深度。 可以以低成本监测凹槽的蚀刻深度，并且获得更高的监视精度。

公开(公告)号：US10818655B2

公开(公告)日：2020-10-27

申请号：US15023049

申请日：2014-12-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng Zhang ,  Sen Zhang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8236 ,  H01L29/08 ,  H01L21/266 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).