公开(公告)号：US10593419B1

公开(公告)日：2020-03-17

申请号：US15894046

申请日：2018-02-12

Applicant: Cadence Design Systems, Inc.

Inventor： Steven Lee Gregor ,  Puneet Arora ,  Norman Robert Card

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G11C29/36

Abstract: Systems and methods disclosed herein provide for improved diagnostics for memory built-in self-test (“MBIST”). Embodiments provide for a sequence iterator unit including a diagnostics analysis unit that monitors and reports on the failing read count associated with the tested memory. Embodiments further provide for a bit fail map report that is generated based on the failing read count.

公开(公告)号：US10586011B1

公开(公告)日：2020-03-10

申请号：US15928627

申请日：2018-03-22

Applicant: Cadence Design Systems, Inc.

Inventor： Dennis Nagle ,  Amit Kumar Sharma ,  Delong Cai ,  Xuegang Zeng ,  Hui Qi

IPC: G06F17/50

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

公开(公告)号：US10586000B1

公开(公告)日：2020-03-10

申请号：US16130027

申请日：2018-09-13

Applicant: Cadence Design Systems, Inc.

Inventor： Anshu Mani ,  Bhuvnesh Kumar ,  Xin Gu

IPC: G06F17/50

Abstract: The present disclosure relates to modeling the transient current of a partially simulated hierarchical gate-level electronic design. Embodiments may include providing a partially simulated hierarchical gate-level electronic design, wherein the design includes a design hierarchy having one or more leaf blocks associated therewith. Embodiments may also include identifying activity of sequential elements of the leaf blocks using simulation vectors, wherein the activity is used to estimate an amount of current associated with the sequential elements. Embodiments may further include computing an adaptive activity of a parent block of the leaf blocks, wherein the adaptive activity of the parent block corresponds to a weighted average of known activity of leaf blocks. Embodiments may also include generating an adaptive activity of a top block of the leaf blocks based upon the adaptive activity of the parent block and performing a mixed-mode simulation based upon the adaptive activity of the top block.

公开(公告)号：US10579470B1

公开(公告)日：2020-03-03

申请号：US16046927

申请日：2018-07-26

Applicant: Cadence Design Systems, Inc.

Inventor： John M. MacLaren ,  Carl Nels Olson

IPC: G06F11/10 ,  G06F3/06

Abstract: Various embodiments provide for a memory controller capable of detecting an error on addressing (address error or address fault) of memory commands for a memory device implementing an inline storage configuration of primary data with associated error checking data. According to some embodiments, the memory controller indicates that an address error of a particular memory command has occurred (or likely occurred) by detecting when a plurality of data errors is produced by a plurality of error checks performed on primary data resulting from the particular memory command. Various embodiments described herein allow both single-bit error detection and correction, and address protection to exist in a memory solution implementing an inline error checking data storage configuration, such as inline ECC storage configuration.

公开(公告)号：US10551431B1

公开(公告)日：2020-02-04

申请号：US15852875

申请日：2017-12-22

Applicant: Cadence Design Systems, Inc.

Inventor： Chung-Do Yang ,  Hoi-Kuen Lam ,  John Mario Wilkosz

IPC: G06F17/50 ,  G01R31/28

Abstract: Described is an improved approach to implement EM analysis, where the analysis can be performed early stages of the design process. Tree-routing is implemented using a structural routing solution, where an automatic routing mechanism is performed to generate a complete routing tree. That routing tree is then used to perform topology-driven EM analysis at various stages of the design process.

公开(公告)号：US10546080B1

公开(公告)日：2020-01-28

申请号：US16233590

申请日：2018-12-27

Applicant: Cadence Design Systems, Inc.

Inventor： Yonatan Ashkenazi ,  Nir Hadaya ,  Tal Tabakman ,  Nadav Chazan ,  Yotam Gil

IPC: G06F17/50 ,  G06N20/00 ,  G06F11/26

Abstract: A method for identifying a potential cause of a failure in simulation runs on a design under test (DUT) using machine learning is disclosed.

公开(公告)号：US10541043B1

公开(公告)日：2020-01-21

申请号：US15421158

申请日：2017-01-31

Applicant: Cadence Design Systems, Inc.

Inventor： Carl Alexander Wisnesky, II ,  Patrick Wayne Gallagher ,  Steven Lee Gregor ,  Norman Robert Card

IPC: G11C29/44 ,  G11C29/12 ,  G06F11/25

Abstract: Embodiments relate generally to a scalable, modularized mechanism which allows for storing programmable data streams on chip and provides repeatable on-demand issuances of data streams to one or more targeted instruments. In some embodiments, multiple data streams are grouped into data stream schedules to perform a series of programmable operations on demand. In these and other embodiments, data stream schedules can be reused and further grouped into data stream plans that can be executed in any order upon request or are hard-coded in a specific order.

公开(公告)号：US10540470B1

公开(公告)日：2020-01-21

申请号：US15585623

申请日：2017-05-03

Applicant: Cadence Design Systems, Inc.

Inventor： Paul W. Kollaritsch

IPC: G06F17/50

Abstract: The present embodiments relate generally to creating power grids for complex integrated circuits having many power domains, macros, and secondary power regions. In some embodiments, a power grid compiler translates a high level description of a power grid into base-level commands that can be used by other tools to implement the wires and vias of the power grid. In these and other embodiments, the high level description comprises a terse, high-level, process technology dependent and design/chip independent language for describing the grid of power and ground wires and vias, including their connections to macros and a multitude of complex power nets that are typical in recent day SOCs. According to certain aspects, the language further allows designers to specify additions/subtractions to the core grid over macros and secondary power instance groups. According to still further aspects, embodiments allow for incremental repairs of only specific portions of the power grid.

公开(公告)号：US10540466B1

公开(公告)日：2020-01-21

申请号：US15893418

申请日：2018-02-09

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Alon Kfir ,  Jennifer Lee

IPC: G06F17/50

Abstract: An exemplary emulation computer may allocate a portion of its emulation memory for capturing probe data during a runtime of emulating a device under test (DUT). The emulation computer may instantiate a plurality of streaming probes from dynamic netlists provided by a user. The streaming probes may capture non-transitory internal signals within the DUT and transmit the captured non-transitory internal signals to the allocated portion of the emulation memory, which in turn may store the received signals as waveform data records. During the runtime of emulating the DUT, the emulation computer may receive an upload request for the waveform data records from a workstation computer. In response to the request, the emulation computer may transmit the waveform data records to the workstation computer. The emulation computer does not have to pause or stop the runtime of emulating the DUT while transmitting the data records to the workstation computer.

公开(公告)号：US10540461B1

公开(公告)日：2020-01-21

申请号：US16038152

申请日：2018-07-17

Applicant: Cadence Design Systems, Inc.

Inventor： Shai Mizrachi ,  Eyal Gvili

IPC: G06F17/50 ,  G06K9/62 ,  G06F16/901

Abstract: A method for functional safety verification for use in a verification of a design under test (DUT), includes obtaining a set of verification tests previously executed on the DUT and related execution data; injecting a fault into each of the tests of the set of verification tests; analyzing a hierarchy tree representation of the DUT from top down to identify clusters of faults under child nodes of the hierarchy tree; and for each of the clusters of faults, based on the execution data, performing test ordering of tests from the set of verification tests according to likelihood of classifying the faults under the child node in which that cluster is located.