公开(公告)号：US07194288B2

公开(公告)日：2007-03-20

申请号：US11201229

申请日：2005-08-09

Applicant: Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

Inventor： Chang-Jae Lee ,  Ki-Seon Ryu ,  Beum-Joon Kim

IPC: H04B1/38

CPC classification number: H04W52/0235 ,  Y02D70/00

Abstract: A method of performing a ranging process between a base station and a mobile station in sleep mode in a wireless access system, wherein the base station provides the mobile station with an initial notification of a periodic ranging time that occurs during a sleep time interval and during which the mobile station is to perform the ranging process, the initial notification included in a first message indicating whether the mobile station should terminate sleep mode to receive downlink data, and wherein the base station provides the mobile station with subsequent notifications of periodic ranging times that occur during the sleep time interval, the subsequent notifications indicated in a second message, the second message transmitted to the mobile station as part of the ranging process such that the mobile station performs a plurality of ranging processes within the sleep time interval.

Abstract translation: 一种在无线接入系统中以休眠模式在基站与移动站之间执行测距过程的方法，其中所述基站向所述移动站提供在睡眠时间间隔期间和在休眠期间期间发生的周期性测距时间的初始通知 移动台将要执行测距过程的初始通知包括在指示移动台是否应当终止睡眠模式以接收下行链路数据的第一消息中，并且其中基站向移动台提供周期性测距时间的后续通知， 在睡眠时间间隔期间发生第二消息中指示的后续通知，将第二消息作为测距过程的一部分发送到移动台，使得移动台在睡眠时间间隔内执行多个测距过程。

公开(公告)号：US06258647B1

公开(公告)日：2001-07-10

申请号：US09041597

申请日：1998-03-13

Applicant: Chang-Jae Lee ,  Jong-Kwan Kim

Inventor： Chang-Jae Lee ,  Jong-Kwan Kim

IPC: H01L218238

CPC classification number: H01L23/535 ,  H01L21/823842 ,  H01L21/823871 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process. Also, by providing a conductive layer between the first and second gates, which electrically connects those gates, mutual diffusion of the impurities doping the polysilicon layers is prevented.

公开(公告)号：US06246087B1

公开(公告)日：2001-06-12

申请号：US09217988

申请日：1998-12-22

Applicant: Chang-Jae Lee ,  Won-Suck Yang

Inventor： Chang-Jae Lee ,  Won-Suck Yang

IPC: H01L27108

CPC classification number: H01L27/10852

Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Abstract translation: 一种用于半导体存储器件的存储单元结构及其制造方法，其适用于需要非常高集成度的256M或更大容量的DRAM存储器件，其包括以下步骤：在半导体衬底上形成顺序的第一和第二随机层 ; 在第二随机层上图案化具有有限线宽度的第一光致抗蚀剂层; 使用图案化的第一光致抗蚀剂层作为掩模来图案化第二随机层; 去除第一光致抗蚀剂层，然后在第二无规层的图案之间图案化具有有限线宽度的第二光致抗蚀剂层; 使用如此构图的第二光致抗蚀剂层作为掩模来图案化第一无规层，以便放置在第二随机层的图案之间; 以及去除所述第二无规层和所述第二光致抗蚀剂层。

公开(公告)号：US6136645A

公开(公告)日：2000-10-24

申请号：US979112

申请日：1997-11-26

Applicant: Woun-Suk Yang ,  Chang-Jae Lee

Inventor： Woun-Suk Yang ,  Chang-Jae Lee

IPC: H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10808

Abstract: A fabrication method for a semiconductor memory device, which forms a capacitor over a bit line, includes the steps of forming an active region pattern on a semiconductor substrate, forming a field oxide region for electrically isolating single devices in the semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a first conductive film to serve as a gate electrode on the gate insulating film, forming a first insulating film having a first etching characteristic on the first conductive film, and patterning the first insulating film and the first conductive film to form a plurality of word line patterns. Next a second insulating film, having the first etching characteristic, is formed over the semiconductor substrate, and is etched to form sidewall spacers at lateral walls of each word line pattern. A third insulating film is then formed over the semiconductor substrate, and removed from regions where a bit line is to be formed. This exposes the active region and forms a bit line trench pattern. A bit line is then formed with portions thereof disposed in the bit line trench pattern, and a capacitor is formed over the bit line. The different etching characteristics of the insulating films allows for a larger contact hole to be formed thereby improving the contact hole aspect ratio.

Abstract translation: 一种用于在位线上形成电容器的半导体存储器件的制造方法包括以下步骤：在半导体衬底上形成有源区域图案，形成用于电绝缘半导体衬底中的单个器件的场氧化物区域，形成栅极 在所述半导体衬底上形成绝缘膜，在所述栅极绝缘膜上形成用作栅电极的第一导电膜，在所述第一导电膜上形成具有第一蚀刻特性的第一绝缘膜，以及将所述第一绝缘膜和所述第一导电 电影以形成多个字线图案。 接下来，在半导体衬底上形成具有第一蚀刻特性的第二绝缘膜，并且被蚀刻以在每个字线图案的侧壁处形成侧壁间隔物。 然后在半导体衬底上形成第三绝缘膜，并从要形成位线的区域中去除。 这暴露了有源区域并形成位线沟槽图案。 然后形成位线，其位置设置在位线沟槽图案中，并且在位线上形成电容器。 绝缘膜的不同蚀刻特性允许形成更大的接触孔，从而改善接触孔纵横比。

公开(公告)号：US6133598A

公开(公告)日：2000-10-17

申请号：US84982

申请日：1998-05-28

Applicant: Chang-Jae Lee ,  Nae-Hak Park

Inventor： Chang-Jae Lee ,  Nae-Hak Park

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L27/10888 ,  H01L27/10811

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract translation: 半导体器件包括半导体衬底，其具有包括晶体管的第一和第二杂质区的有源区，形成在半导体衬底的有源区上且与半导体衬底隔离的栅极;形成在半导体衬底上的第一绝缘层， 分别暴露第一和第二杂质区的第一和第二接触孔，具有存储电极和平板电极的电容器，所述存储电极通过所述第一接触孔电连接到所述第一杂质区，位线接触焊盘连接 通过第二接触孔电连接到第二杂质区，形成在平板电极上并具有暴露位线接触焊盘的第三接触孔的第二绝缘中间层和形成在第二绝缘中间层上并与位接触的位线 线接触垫通过第三接触孔。

公开(公告)号：US5959321A

公开(公告)日：1999-09-28

申请号：US901876

申请日：1997-07-29

Applicant: Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

Inventor： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

IPC: G11C11/34 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10844 ,  H01L27/10805

Abstract: A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

Abstract translation: 动态随机存取存储器（DRAM）被组织为具有电容器对的基本组织单元的矩阵。 每个电容器对具有第一电容器和其中的第二电容器之一。 每个基本组织单元布置如下：在基板上形成作为平行线的第一字线和第二字线; 第一字线位于第一掺杂区和第二掺杂区之间，以限定第一晶体管; 第二字线位于第一晶体管的第二掺杂区域和第三掺杂区域之间，以限定第二晶体管; 位线以与第一字线和第二字线成倾斜的角度位于衬底的第二掺杂区域上; 第一电容器覆盖第一掺杂区域和第一字线，基本上位于第一掺杂区域的中心，经由第一接触孔连接到第一掺杂区域，并且具有六边形平面部分; 覆盖第三掺杂区域和第二字线的第二电容器基本上位于第三掺杂区域的中心，经由第二接触孔连接到第三掺杂区域，并且具有六边形平面部分; 并且基本组织单元的第一掺杂区域，第二掺杂区域和第三掺杂区域中的每一个的中心点可通过假想直线特征线连接。

公开(公告)号：US5830791A

公开(公告)日：1998-11-03

申请号：US871779

申请日：1997-06-09

Applicant: Chang Jae Lee ,  Oh Seok Han

Inventor： Chang Jae Lee ,  Oh Seok Han

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10808

Abstract: A semiconductor memory cell has a semiconductor substrate, an active region disposed on the semiconductor substrate and having two impurity regions, a gate electrode disposed on the active region, a field region isolated from the active region on the semiconductor substrate and having a contract hole, a capacitor disposed over the active region and field region on the semiconductor substrate, and a buried region disposed under the field region and the bit line contacting the first impurity region through the contact hole.

Abstract translation: 半导体存储单元具有半导体衬底，设置在半导体衬底上并具有两个杂质区的有源区，设置在有源区上的栅电极，与半导体衬底上的有源区隔离并具有收缩孔的场区， 设置在半导体衬底上的有源区域和场区上的电容器，以及设置在场区域下方的掩埋区域和通过接触孔与第一杂质区域接触的位线。

公开(公告)号：US5721155A

公开(公告)日：1998-02-24

申请号：US520434

申请日：1995-08-29

Applicant: Chang Jae Lee

Inventor： Chang Jae Lee

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/31

CPC classification number: H01L21/76885

Abstract: A method for forming a via contact of a semiconductor device includes the steps of forming a first insulating layer on a substrate, forming a lower conducting layer on the first insulating layer, forming a third insulating layer on the lower conducting layer, forming a first photoresist on the third insulating layer, etching the third insulating layer to form a via pillar, removing the first photoresist, forming a second photoresist on the via pillar and the lower conducting layer, etching the second photoresist except on the via pillar and a portion of the lower conducting layer, forming a metal line by removing portions of the lower conducting layer from which the second photoresist has been etched, removing the second photoresist that has not been etched, forming a second insulating layer on the metal line, the first insulating layer, and the via pillar, etching the second insulating layer to expose an upper surface of the via pillar, etching the via pillar to thereby form a via hole through the second insulating layer, and forming an upper conducting layer on the second insulating layer, through the via hole, and in contact with the lower conducting layer.

Abstract translation: 一种用于形成半导体器件的通孔接触的方法包括以下步骤：在衬底上形成第一绝缘层，在第一绝缘层上形成下导电层，在下导电层上形成第三绝缘层，形成第一光致抗蚀剂 在所述第三绝缘层上蚀刻所述第三绝缘层以形成通孔，除去所述第一光致抗蚀剂，在所述通孔柱和所述下导电层上形成第二光致抗蚀剂，蚀刻除所述通孔柱之外的所述第二光致抗蚀剂， 下导电层，通过去除蚀刻第二光致抗蚀剂的下导电层的部分，去除未被蚀刻的第二光致抗蚀剂，在金属线上形成第二绝缘层，形成金属线，第一绝缘层， 和通孔柱，蚀刻第二绝缘层以暴露通孔柱的上表面，蚀刻通孔柱，从而形成通孔 e通过第二绝缘层，并且在第二绝缘层上形成上导电层，通过通孔，并与下导电层接触。

公开(公告)号：US5686344A

公开(公告)日：1997-11-11

申请号：US582904

申请日：1996-01-04

Applicant: Chang-Jae Lee

Inventor： Chang-Jae Lee

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/0921 ,  H01L21/76221 ,  H01L21/763 ,  Y10S148/05

Abstract: An improved device isolation method for a semiconductor device capable of independently and compatibly providing an isolation film in the interior of well and an isolation film between wells during a consistent process, so that latch-up characteristic can be improved even in a device requiring a design rule of below 0.5 .mu.m, which includes a first step which combines a second step which forms a device isolation film within a well and a third step which forms a device isolation film between wells, the second and third steps being compatible to each other during the same step.

Abstract translation: 一种用于半导体器件的改进的器件隔离方法，其能够在一致的过程中独立且兼容地在阱内部提供隔离膜和阱之间的隔离膜，使得即使在需要设计的器件中也可以提高闩锁特性 规定在0.5μm以下，其包括第一步骤，其组合在孔内形成器件隔离膜的第二步骤和在阱之间形成器件隔离膜的第三步骤，第二和第三步骤在 同样的一步。

公开(公告)号：US5686339A

公开(公告)日：1997-11-11

申请号：US689155

申请日：1996-07-30

Applicant: Chang-Jae Lee ,  Hwan Myeong Kim

Inventor： Chang-Jae Lee ,  Hwan Myeong Kim

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L28/40

Abstract: A method for fabricating a capacitor of a semiconductor device, includes the steps of: forming a first insulating layer and then a second insulating layer on the first insulating layer; removing the second insulating layer of a first electrode region of a capacitor; forming a side wall at a side of the second insulating layer; etching the first insulating layer by using the side wall of the second insulating layer as a mask so as to form a contact hole; forming a first electrode of a capacitor on the side wall and on the contact hole; forming a dielectric layer on the first electrode of the capacitor; and forming a second electrode of the capacitor on the dielectric layer. And, a capacitor in a semiconductor device includes: a substrate; a first insulating layer being formed at an upper part of the substrate 20 and having a contact hole; a second insulating layer being formed at an upper part of the first insulating layer; side walls being formed at an upper part of the first insulating layer and at a side surface of the second insulating layer both in an arc-shape; a first electrode of a capacitor being formed on the contact hole and the side walls; a dielectric layer formed on the first electrode of the capacitor; and a second electrode of the capacitor being formed on the first electrode of the capacitor.

Abstract translation: 一种制造半导体器件的电容器的方法，包括以下步骤：在第一绝缘层上形成第一绝缘层，然后形成第二绝缘层; 去除电容器的第一电极区域的第二绝缘层; 在所述第二绝缘层的一侧形成侧壁; 通过使用第二绝缘层的侧壁作为掩模蚀刻第一绝缘层，以形成接触孔; 在侧壁和接触孔上形成电容器的第一电极; 在所述电容器的所述第一电极上形成介电层; 以及在所述电介质层上形成所述电容器的第二电极。 并且，半导体器件中的电容器包括：衬底; 第一绝缘层，形成在基板20的上部并具有接触孔; 第二绝缘层，形成在所述第一绝缘层的上部; 在所述第一绝缘层的上部和所述第二绝缘层的侧面形成为弧形的侧壁; 电容器的第一电极形成在接触孔和侧壁上; 形成在电容器的第一电极上的电介质层; 并且电容器的第二电极形成在电容器的第一电极上。