公开(公告)号：US5300463A

公开(公告)日：1994-04-05

申请号：US847368

申请日：1992-03-06

申请人： David A. Cathey ,  J. Brett Rolfson

发明人： David A. Cathey ,  J. Brett Rolfson

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/02 ,  H01L21/465

CPC分类号： H01L21/31111

摘要： A method of utilizing and etching SiO.sub.2 in the processing of semiconductor wafers comprises: a) providing a layer of undoped SiO.sub.2 atop a wafer; b) providing a layer of doped SiO.sub.2 atop the layer of undoped SiO.sub.2 ; and c) wet etching the layer of doped SiO.sub.2 selectively relative to the undoped layer of SiO.sub.2 utilizing an acid solution, the acid solution comprising a mixture of at least two different mineral acids provided in a selected ratio relative to one another, one of the mineral acids being HF. The preferred volumetric ratio of other mineral acids in the acid solution to HF in the acid solution is from 20:1 to 110:1, with a ratio of from 45:1 to 65:1 being most preferred. Example acids to be combined with the HF include H.sub.2 SO.sub.4, HCl, HNO.sub.3, H.sub.3 PO.sub.4, HBr, HI, HClO.sub.4, and HIO.sub.4, or mixtures thereof.

摘要翻译： 在半导体晶片的处理中利用和蚀刻SiO 2的方法包括：a）在晶片顶上提供未掺杂的SiO 2层; b）在未掺杂的SiO 2层的顶部提供掺杂SiO 2层; 和c）使用酸溶液相对于未掺杂的SiO 2层选择性地浸蚀掺杂SiO 2层，所述酸溶液包含以相对于彼此的选定比率提供的至少两种不同的无机酸的混合物，所述矿物质之一 酸是HF。 在酸溶液中酸溶液中的其它无机酸与HF的优选体积比为20:1至110:1，最优选的比例为45:1至65:1。 与HF组合的实例酸包括H 2 SO 4，HCl，HNO 3，H 3 PO 4，HBr，HI，HClO 4和HIO 4，或其混合物。

公开(公告)号：US5240796A

公开(公告)日：1993-08-31

申请号：US727834

申请日：1991-07-09

申请人： Ruojia Lee ,  J. Brett Rolfson

发明人： Ruojia Lee ,  J. Brett Rolfson

IPC分类号： G03F1/34

CPC分类号： G03F1/34

摘要： A method of fabricating a chromeless phase shift reticle. The method includes the steps of: depositing a layer of material on a transparent substrate to a thickness of "t"; patterning and anisotropically etching the material to form a pattern of openings to the substrate; depositing a phase shifter material over the layer of material and into the openings; polishing by chemical mechanical planarization (CMP) the phase shifter material; and selectively wet etching the initially deposited layer of material. This process forms a chromeless phase shift reticle having a pattern of phase shifters of a thickness of "t" with a pattern of light transmissive areas on the substrate therebetween. The thickness "t" and a phase shifter material index of refraction may be selected to achieve a 180.degree. phase shift between light transmitted through a phase shifter relative to light transmitted through a light transmissive area on the substrate.

摘要翻译： 一种制造无铬相移掩模版的方法。 该方法包括以下步骤：在透明衬底上沉积厚度为“t”的材料层; 图案化和各向异性地蚀刻材料以形成到基板的开口图案; 在所述材料层上沉积移相器材料并进入所述开口中; 通过化学机械平面化（CMP）抛光移相器材料; 并选择性地湿蚀刻初始沉积的材料层。 该过程形成具有厚度为“t”的移相器图案的无铬相移掩模版，并且其上的基板上具有透光区域的图案。 可以选择厚度“t”和移相器材料折射率来实现透射通过移相器的光相对于透射通过衬底上的透光区域的光的180度相移。

公开(公告)号：US5229331A

公开(公告)日：1993-07-20

申请号：US837453

申请日：1992-02-14

申请人： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

发明人： Trung T. Doan ,  J. Brett Rolfson ,  Tyler A. Lowrey ,  David A. Cathey

IPC分类号： H01J1/304 ,  H01J9/02 ,  H01L21/3105

CPC分类号： H01J9/025 ,  H01L21/31053 ,  H01J2201/30426 ,  H01J2201/319 ,  H01J2209/0226

摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.

摘要翻译： 用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积 具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii） 化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料 。

公开(公告)号：US5194346A

公开(公告)日：1993-03-16

申请号：US687036

申请日：1991-04-15

申请人： J. Brett Rolfson ,  David A. Cathey, Jr.

发明人： J. Brett Rolfson ,  David A. Cathey, Jr.

IPC分类号： G03F1/30

CPC分类号： G03F1/30

摘要： A method of fabricating phase shifting reticles that can be used as a mask in photolithographic processes such as semiconductor wafer patterning. An opaque film such as chromium is first deposited on a transparent substrate. The opaque film is then patterned with openings by a first photolithographic process. A phase shifter material such as (SiO.sub.2) is then blanket deposited into the openings and over the opaque film. The phase shifter material is then polished by chemical mechanical planarization (CMP) to a thickness "T" which is selected to produce a 180.degree. phase shift. The phase shifter material is then photopatterned and selectively etched by a second photolithographic process to remove all of the phase shifter material except in every other opening formed in the opaque film. This forms a repetitive pattern of alternating phase shifters and light transmission openings through the opaque film.

摘要翻译： 制造可用作诸如半导体晶片图案化的光刻工艺中的掩模的相移掩模版的方法。 首先将诸如铬的不透明膜沉积在透明基底上。 然后通过第一光刻工艺将不透明膜用开口图案化。 然后将诸如（SiO 2）的移相器材料被覆盖地沉积到开口中并在不透明膜上方。 然后通过化学机械平面化（CMP）将移相器材料抛光至选择为产生180°相移的厚度“T”。 然后通过第二光刻工艺对移相器材料进行光图案化并选择性地蚀刻，以除去除了不透明膜中形成的每隔一个开口以外的所有移相器材料。 这形成了通过不透明膜的交替移相器和光透射开口的重复图案。

公开(公告)号：US20100040962A1

公开(公告)日：2010-02-18

申请号：US12581455

申请日：2009-10-19

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F1/00

CPC分类号： G03F1/32 ,  G03F1/29

摘要： The present invention provides an attenuated phase shift mask (“APSM”) that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions corresponding to isolated device features, highly attenuated regions at the edges of completely transmissive regions corresponding to closely spaced or nested device features, and completely opaque areas where it is desirable to block transmission of all radiation through the APSM. The present invention further provides methods for fabricating the APSMs according to the present invention.

摘要翻译： 本发明提供了衰减相移掩模（“APSM”），其在每个实施例中包括尺寸和形状以确定期望的半导体器件特征的完全透射区域，在完全透射区域的边缘处对应于隔离的器件特征的略微衰减的区域 在完全透射区域的边缘处的高度衰减的区域对应于紧密间隔或嵌套的器件特征，以及完全不透明的区域，其中期望阻止通过APSM的所有辐射的透射。 本发明还提供了制造根据本发明的APSM的方法。

公开(公告)号：US07338609B2

公开(公告)日：2008-03-04

申请号：US11333678

申请日：2006-01-17

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： B44C1/22 ,  C25F3/00 ,  G03F1/00

CPC分类号： G03F1/40 ,  G03F1/86

摘要： A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask substrate to expose the underlying chrome layer. The selective removal leaves at least one tab of photoresist edge bead over the chrome layer. After the first e-beam mask writing step and subsequent etch, the tab can be removed to expose a portion of the chromium layer that can act as a new ground point for a second e-beam etch. Also, a nozzle for use in selectively removing the edge bead to leave a tab of photoresist edge bead.

摘要翻译： 通过选择性地去除光掩模衬底的光致抗蚀剂边缘以暴露下面的铬层来为第二或随后的电子束掩模写入步骤提供接地点的方法。 选择性去除在铬层上留下光致抗蚀剂边缘珠的至少一个突片。 在第一电子束掩模写入步骤和随后的蚀刻之后，可以去除突片以暴露可以充当第二电子束蚀刻的新接地点的铬层的一部分。 而且，用于选择性地去除边缘珠以留下光致抗蚀剂边缘珠的突片的喷嘴。

公开(公告)号：US07262123B2

公开(公告)日：2007-08-28

申请号：US10903348

申请日：2004-07-29

申请人： John Aiton ,  Joseph M. Richards ,  J. Brett Rolfson ,  John M. Drynan

发明人： John Aiton ,  Joseph M. Richards ,  J. Brett Rolfson ,  John M. Drynan

IPC分类号： H01L21/44

CPC分类号： H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/49431 ,  H01L2224/78301 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable material over the metal-containing layer. The radiation-imageable material can be configured as a multi-level pattern having a first topographical region with a first elevational height and a second topographical region with a second elevational height above the first elevational height. The second topographical region can be laterally displaced from the bonding region by at least a lateral width of the first topographical region, with said lateral width being at least about 10 microns. Additionally, or alternatively, the elevational height of the second topographical region can be at least about 2 microns above the elevational height of the first topographical region. The invention also includes a method of forming wire bonds for semiconductor constructions in which a multi-level pattern is photolithographically formed in a radiation-imageable material (such as, for example, polyimide).

摘要翻译： 本发明包括一种半导体结构，其具有与含金属层相关联的引线接合区域，并且在含金属层之上具有可辐射成像材料。 可辐射成像材料可以被配置为具有具有第一高度的第一形貌区域和具有高于第一高度高度的第二高度高度的第二地形区域的多层图案。 第二形貌区域可以从接合区域横向移位至少第一形貌区域的横向宽度，所述横向宽度为至少约10微米。 另外或替代地，第二形貌区域的高度高度可以高于第一地形区域的高度高度至少约2微米。 本发明还包括一种形成用于半导体结构的引线键合的方法，其中在可辐射成像材料（例如，聚酰亚胺）中光刻形成多层图案。

公开(公告)号：US07057263B2

公开(公告)日：2006-06-06

申请号：US10734419

申请日：2003-12-11

申请人： John T. Moore ,  Scott Jeffrey DeBoer ,  Mark Fischer ,  J. Brett Rolfson ,  Annette L. Martin ,  Ardavan Niroomand

发明人： John T. Moore ,  Scott Jeffrey DeBoer ,  Mark Fischer ,  J. Brett Rolfson ,  Annette L. Martin ,  Ardavan Niroomand

IPC分类号： H01L23/58

CPC分类号： H01L21/0217 ,  G03F7/091 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3185

摘要： In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer. In another aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; c) forming a photoresist over and against the barrier layer; d) exposing the photoresist to a patterned beam of light to render at least one portion of the photoresist more soluble in a solvent than an other portion, the barrier layer being an antireflective surface that absorbs light passing through the photoresist; and e) exposing the photoresist to the solvent to remove the at least one portion while leaving the other portion over the barrier layer. In yet another aspect, the invention includes a semiconductor wafer assembly, comprising: a) a silicon nitride material, the material having a surface; b) a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) a photoresist over and against the barrier layer.

公开(公告)号：US07018936B2

公开(公告)日：2006-03-28

申请号：US10756622

申请日：2004-01-12

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： H01L21/302

CPC分类号： H01L21/31133 ,  H01L21/0273

摘要： A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness. The ion implanted regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask.

摘要翻译： 掩模和蚀刻半导体衬底的方法包括在半导体衬底上形成待蚀刻的层。 在待蚀刻的层上形成成像层。 去除成像层的选定区域以留下仅部分地延伸到成像层中的开口图案。 在去除之后，使用成像层作为蚀刻掩模蚀刻待蚀刻的层。 在一个实施方案中，处理半导体的离子注入光刻方法包括在半导体衬底上形成待蚀刻的层。 在待蚀刻层上形成所选厚度的成像层。 成像层的选定区域被离子注入以改变注入区域对成像层的非注入区域的溶剂溶解度，其中所选择的区域不完全延伸穿过成像层厚度。 去除成像层的离子注入区域以留下仅部分地延伸到成像层中的开口图案。 在去除之后，使用成像层作为蚀刻掩模蚀刻待蚀刻的层。

公开(公告)号：US06979528B2

公开(公告)日：2005-12-27

申请号：US10314857

申请日：2002-12-09

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： B05C11/00 ,  B05C13/00 ,  G03F7/16 ,  G03F7/38 ,  G03F7/40 ,  H01L21/00 ,  G03F7/26

CPC分类号： H01L21/67103 ,  F28D2021/0077 ,  G03F7/168 ,  G03F7/38 ,  G03F7/40 ,  H01L21/67109

摘要： A method and apparatus for baking a film onto a substrate. A film, such as a layer of photoresist, is disposed on a first surface of a substrate while a second surface is exposed to a liquid bath. The liquid bath is maintained at a pre-selected temperature. Exposure of the substrate to the liquid bath allows the film on the opposite surface to bake. The liquid bath is then re-circulated to maintain a constant and uniform temperature gradient across the substrate.

摘要翻译： 一种将薄膜烘烤在基材上的方法和装置。 将诸如光致抗蚀剂层的膜设置在基板的第一表面上，同时将第二表面暴露于液槽。 液浴保持在预先选定的温度。 将基板暴露于液槽允许相对表面上的膜被烘烤。 然后液体浴再次循环，以保持基板上恒定均匀的温度梯度。