公开(公告)号：US06258689B1

公开(公告)日：2001-07-10

申请号：US09626328

申请日：2000-07-26

Applicant: Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

Inventor： Gary B. Bronner ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Rick L. Mohler ,  Carl Radens ,  William R. Tonti

IPC: H01L2120

CPC classification number: H01L27/10861 ,  H01L29/66181

Abstract: Trench capacitors are fabricated utilizing a method which results in a metallic nitride as a portion of a node electrode in a lower region of the trench. The metallic nitride-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell layouts and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells having various trench configuration and design.

Abstract translation: 使用导致在沟槽的下部区域中作为节点电极的一部分的金属氮化物的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含金属氮化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元布局和/或降低的单元访问时间。 本发明的沟槽电容器特别可用作具有各种沟槽结构和设计的DRAM存储单元的组件。

公开(公告)号：US06252271B1

公开(公告)日：2001-06-26

申请号：US09097515

申请日：1998-06-15

Applicant: Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Donald C. Wheeler

Inventor： Jeffrey P. Gambino ,  Louis L. Hsu ,  Jack A. Mandelman ,  Donald C. Wheeler

IPC: H01L29788

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

Abstract: A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall having a slope angle greater than the slope angle of the first sidewall. Thereafter, a polysilicon spacer is formed on the second sidewall while simultaneously removing the polysilicon on the first sidewall. The polysilicon spacer forms a floating gate which is surrounded on a plurality of sides by the second sidewall.

公开(公告)号：US06222219B1

公开(公告)日：2001-04-24

申请号：US09183416

申请日：1998-10-30

Applicant: Jeffrey P. Gambino ,  David E. Kotecki

Inventor： Jeffrey P. Gambino ,  David E. Kotecki

IPC: H01L27108

CPC classification number: H01L27/10852

Abstract: A structure and process for fabricating a crown capacitor using a tapered etch and chemical mechanical polishing to form a bottom electrode having an increased area and crown is provided. The tapered etch is used to form a trough in an interlevel dielectric, e.g. SiO2, and is performed over contact hole forming a crown-like structure. The trough and, optionally, the crown are then covered by a conductor, which is patterned by chemical mechanical polishing.

Abstract translation: 提供了使用锥形蚀刻和化学机械抛光来制造冠状电容器以形成具有增加的面积和凸度的底部电极的结构和工艺。 锥形蚀刻用于在层间电介质中形成槽。 SiO 2，并且在形成冠状结构的接触孔上进行。 槽和任选的表冠然后由导体覆盖，导体通过化学机械抛光图案化。

公开(公告)号：US06177348B1

公开(公告)日：2001-01-23

申请号：US09009446

申请日：1998-01-20

Applicant: Jeffrey P. Gambino ,  Peter D. Hoh ,  Mark A. Jaso ,  Ernest N. Levine

Inventor： Jeffrey P. Gambino ,  Peter D. Hoh ,  Mark A. Jaso ,  Ernest N. Levine

IPC: H01L2144

CPC classification number: H01L21/76882 ,  Y10S438/926

Abstract: A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Abstract translation: 一种用于在表面上沉积材料的方法，具有以下步骤：a）获得其上具有至少特征的表面，所述表面和所述特征具有沉积在其上的第一材料层，所述第一材料基本上不填充所述特征; b）在第一材料上沉积第二材料层，其中第二材料的熔点小于第一材料的熔点，并且其中第一材料在小于熔点的温度下可溶于第二材料 的第一种材料; 和c）将所述表面加热到至少等于所述第二材料的熔点并且至多等于所述第一材料的熔点的第一温度，其中基本上所有所述通孔都填充有所述第一材料。

公开(公告)号：US6136686A

公开(公告)日：2000-10-24

申请号：US897172

申请日：1997-07-18

Applicant: Jeffrey P. Gambino ,  Mark Jaso ,  Hing Wong

Inventor： Jeffrey P. Gambino ,  Mark Jaso ,  Hing Wong

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/4763

CPC classification number: H01L21/76825 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76897 ,  H01L27/10882 ,  H01L27/10894

Abstract: Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.

Abstract translation: 通过例如蚀刻停止层或植入来提供层的差分蚀刻允许根据阻挡掩模（其不需要高准确度的配准）来执行第二槽蚀刻，以提供槽或凹槽 不同深度的绝缘子层。 当通过金属沉积填充凹槽或凹槽时，根据镶嵌工艺通过平面化图案化，可以实现和优化不同厚度的结构坚固的导体并且被优化以增强集成电路的不同功能区域中的抗噪声和/或信号传播速度，例如 作为动态随机存取存储器的所谓阵列和支持部分。

公开(公告)号：US6090671A

公开(公告)日：2000-07-18

申请号：US941600

申请日：1997-09-30

Applicant: Karanam Balasubramanyam ,  Martin Gall ,  Jeffrey P. Gambino ,  Jack A. Mandelman

Inventor： Karanam Balasubramanyam ,  Martin Gall ,  Jeffrey P. Gambino ,  Jack A. Mandelman

IPC: H01L21/26 ,  H01L21/28 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/28176 ,  H01L21/324 ,  H01L27/10873 ,  Y10S438/91

Abstract: Reduction of gate-induced-drain-leakage in metal oxide semiconductor (MOS) devices is achieved by performing an anneal in a non-oxidizing ambient. In one embodiment, the anneal is performed in a argon and/or ammonia ambients after gate sidewall oxidation that forms the spacers.

Abstract translation: 通过在非氧化性环境中进行退火来实现金属氧化物半导体（MOS）器件中栅极引起的漏极泄漏的减少。 在一个实施例中，在形成间隔物的栅极侧壁氧化之后，在氩气和/或氨气氛中进行退火。

公开(公告)号：US6028004A

公开(公告)日：2000-02-22

申请号：US3101

申请日：1998-01-06

Applicant: Gary B. Bronner ,  Jeffrey P. Gambino

Inventor： Gary B. Bronner ,  Jeffrey P. Gambino

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76838 ,  H01L21/76877 ,  H01L21/76885

Abstract: Electrical interconnection with studs is formed by depositing conductive stud material in contact holes in a dielectric layer; patterning the conductive stud material and removing a shallow portion of the dielectric layer surrounding the stud material; depositing a thin layer of dielectric material over the conductive stud and first dielectric layer; forming a trench in the dielectric layers and over the top of the stud material; and depositing conductive material in the trench.

Abstract translation: 通过在电介质层的接触孔中沉积导电柱状材料形成与螺柱的电互连; 图案化导电柱状材料并去除围绕螺柱材料的介电层的浅部分; 在导电柱和第一介电层上沉积介电材料层; 在电介质层中并在螺柱材料的顶部上形成沟槽; 并在沟槽中沉积导电材料。

公开(公告)号：US5338702A

公开(公告)日：1994-08-16

申请号：US9511

申请日：1993-01-27

Applicant: Edward Kobeda ,  Jeffrey P. Gambino ,  George G. Gifford ,  Nickolas J. Mazzeo

Inventor： Edward Kobeda ,  Jeffrey P. Gambino ,  George G. Gifford ,  Nickolas J. Mazzeo

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L21/302

CPC classification number: H01L21/32136 ,  H01L21/31138 ,  H01L21/76895 ,  Y10S438/97

Abstract: The present invention provides a method for fabricating tungsten local interconnections in high density CMOS circuits, and also provides high density CMOS circuits having local interconnections formed of tungsten. Pursuant to the method, an etch stop layer of chromium is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten is non-selectively deposited on the chromium layer. A photoresist mask is then lithographically patterned over the tungsten layer. The tungsten layer is then etched down to, and stopping at, the chromium layer, after which the photoresist mask is stripped. The stripping preferably uses a low temperature plasma etch in O.sub.2 at a temperature of less than 100.degree. C. Finally, a directional O.sub.2 reactive ion etch is used to remove the chromium layer selectively to the silicon substrate. Borderless contacts are formed with the aid of the chromium etch stop layer beneath the tungsten local interconnection layer. The method of integration of this approach results in anisotropic metal lines patterned over topography using a standard photoresist mask. This approach also allows partial overlap of contacts to reduce device dimensions, and thereby results in improved density and performance.

Abstract translation: 本发明提供一种用于在高密度CMOS电路中制造钨局部互连的方法，并且还提供具有由钨形成的局部互连的高密度CMOS电路。 根据该方法，最初在CMOS硅衬底的电路元件上沉积铬的蚀刻停止层。 接下来，钨层的导电层被非选择性地沉积在铬层上。 然后光致抗蚀剂掩模在钨层上被光刻图案化。 然后将钨层蚀刻到铬层上并停止在其上，之后剥离光致抗蚀剂掩模。 剥离优选在低于100℃的温度下在O 2中使用低温等离子体蚀刻。最后，使用定向O 2反应离子蚀刻来选择性地将硅层除去到硅衬底。 借助于钨局部互连层下方的铬蚀刻停止层形成无边界接触。 该方法的集成方法导致使用标准光致抗蚀剂掩模在地形图上形成的各向异性金属线。 该方法还允许触点的部分重叠以减少器件尺寸，从而导致改善的密度和性能。

公开(公告)号：US5266504A

公开(公告)日：1993-11-30

申请号：US857862

申请日：1992-03-26

Applicant: Jeffrey L. Blouse ,  Jack O. Chu ,  Brian Cunningham ,  Jeffrey P. Gambino ,  Louis L. Hsu ,  David E. Kotecki ,  Seshadri Subbanna ,  Zu-Jean Tien

Inventor： Jeffrey L. Blouse ,  Jack O. Chu ,  Brian Cunningham ,  Jeffrey P. Gambino ,  Louis L. Hsu ,  David E. Kotecki ,  Seshadri Subbanna ,  Zu-Jean Tien

IPC: H01L21/20 ,  H01L21/331 ,  H01L21/365

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66242 ,  Y10S148/124

Abstract: A method of manufacturing a bipolar transistor by use of low temperature emitter process is disclosed. After completion of the usual base and collector formation in a vertical bipolar transistor, an emitter opening is etched in the insulator layer over the base layer at selected locations. A thin layer (less than 500 .ANG.) of in-situ doped amorphous silicon is deposited over the substrate and heated to densify for 30 to 60 minutes at about 650.degree. C. Subsequently an in-situ doped polysilicon layer of 100 to 200 nm is deposited over the amorphous Si film preferably at about 600.degree. C. Subsequently the layers are heated below 600.degree. C. for several hours to convert partially the amorphous Si into a monocrystalline emitter layer over the base regions.

Abstract translation: 公开了一种通过使用低温发射器工艺制造双极晶体管的方法。 在垂直双极晶体管中完成通常的基极和集电极形成之后，在选定位置的基极层上的绝缘体层中蚀刻发射极开口。 原位掺杂非晶硅的薄层（小于500安格姆）沉积在衬底上，并在约650℃下加热至致密化30至60分钟。随后，100-200nm的原位掺杂多晶硅层为 沉积在非晶Si膜上，优选在约600℃。随后将这些层在600℃以下加热数小时，以将非晶硅部分地转变成基底区域上的单晶发射极层。

公开(公告)号：US5154514A

公开(公告)日：1992-10-13

申请号：US751490

申请日：1991-08-29

Applicant: Jeffrey P. Gambino ,  Louis L. Hsu ,  Michael A. Lee ,  Krishna Seshan ,  Alvin Sugerman ,  Francis E. Turene

Inventor： Jeffrey P. Gambino ,  Louis L. Hsu ,  Michael A. Lee ,  Krishna Seshan ,  Alvin Sugerman ,  Francis E. Turene

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: A temperature sensor, comprising: a diode structure including, a) a silicon substrate, b) a first region of a metal silicide in the silicon substrate, c) a second region of a metal-oxide semiconductor material on the first region, d) a third region of a metal over the second region; and, means for using the diode structure as a temperature sensitive device to measure an ambient temperature. The metal-oxide semiconductor material is preferably selected to have a bandgap of not less than about 3.0 eV.

Abstract translation: 1.一种温度传感器，包括：二极管结构，包括：a）硅衬底，b）所述硅衬底中的金属硅化物的第一区域，c）所述第一区域上的金属氧化物半导体材料的第二区域，d） 第二区域上的金属的第三区域; 以及用于使用二极管结构作为温度敏感设备来测量环境温度的装置。 金属氧化物半导体材料优选选择为具有不小于约3.0eV的带隙。