中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

126 records (took 0.031 seconds)

    Silicide strapping in imager transfer gate device
    81.
    发明授权
    Silicide strapping in imager transfer gate device 有权
    成像器中的硅化物贴带传输门装置

    公开(公告)号：US07675097B2

    公开(公告)日：2010-03-09

    申请号：US11565801

    申请日：2006-12-01

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC: H01L27/146

    CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

    Recessed gate for a CMOS image sensor
    83.
    发明授权
    Recessed gate for a CMOS image sensor 有权
    CMOS图像传感器的嵌入式门

    公开(公告)号：US07572701B2

    公开(公告)日：2009-08-11

    申请号：US11735223

    申请日：2007-04-13

    Applicant: James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

    Inventor： James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

    IPC: H01L21/02 ,  H01L31/113

    CPC classification number: H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

    Abstract: A novel CMOS image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate having an upper surface, a gate comprising a dielectric layer formed on the substrate and a gate conductor formed on the gate dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. A portion of the bottom of the gate conductor is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region thereby eliminating any potential barrier interference caused by the pinning layer.

    Abstract translation: 一种新颖的CMOS图像传感器单元结构及其制造方法。 成像传感器包括具有上表面的基板，包括形成在基板上的电介质层的栅极和形成在栅极电介质层上的栅极导体，形成在基板表面附近的第一导电类型的集合阱层 栅极导体的第一侧，形成在基板表面上的集电阱顶部的第二导电类型的钉扎层，以及邻近栅极导体的第二侧形成的第一导电类型的扩散区域，栅极导体形成沟道 收集阱层和扩散区域之间的区域。 栅极导体的底部的一部分在衬底的表面下方凹进。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到深度，使得收集阱与沟道区相交，从而消除由钉扎层引起的任何潜在的屏障干扰。

    Pixel sensor having doped isolation structure sidewall
    84.
    发明授权
    Pixel sensor having doped isolation structure sidewall 有权
    具有掺杂隔离结构侧壁的像素传感器

    公开(公告)号：US07491561B2

    公开(公告)日：2009-02-17

    申请号：US11563531

    申请日：2006-11-27

    Applicant: James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    Inventor： James W. Adkisson ,  Mark D. Jaffe ,  Robert K. Leidy

    IPC: H01L21/84

    CPC classification number: H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14683

    Abstract: A novel pixel sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation structure is formed adjacent to the photosensitive device pinning layer. The trench isolation structure includes a dopant region comprising material of the first conductivity type selectively formed along a sidewall of the isolation structure that is adapted to electrically couple the surface pinning layer to the underlying substrate. The corresponding method for forming the dopant region selectively formed along the sidewall of the isolation structure comprises an out-diffusion process whereby dopant materials present in a doped material layer formed along selected portions in the trench are driven into the underlying substrate during an anneal. Alternately, or in conjunction, an angled ion implantation of dopant material in the isolation structure sidewall may be performed by first fabricating a photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material.

    Abstract translation: 形成在第一导电类型的衬底上的新型像素传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。 在光敏器件钉扎层附近形成沟槽隔离结构。 沟槽隔离结构包括掺杂区域，该掺杂剂区域包括沿着隔离结构的侧壁选择性地形成的第一导电类型的材料，其适于将表面钉扎层电耦合到下面的衬底。 用于形成沿着隔离结构的侧壁选择性地形成的掺杂剂区域的相应方法包括外扩散工艺，由此在退火期间，存在于沿着沟槽中的选定部分形成的掺杂材料层中的掺杂剂材料被驱动到下面的衬底中。 替代地或结合地，隔离结构侧壁中的掺杂剂材料的成角度的离子注入可以通过首先制造光致抗蚀剂层并通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来执行。

    PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES
    86.
    发明申请
    PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES 有权
    用于收集电子和孔的像素传感器单元

    公开(公告)号：US20080272400A1

    公开(公告)日：2008-11-06

    申请号：US12172309

    申请日：2008-07-14

    Applicant: James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    Inventor： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

    IPC: H01L31/00

    CPC classification number: H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

    Abstract: The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

    Abstract translation: 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

    SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE
    87.
    发明申请
    SILICIDE STRAPPING IN IMAGER TRANSFER GATE DEVICE 有权
    图像转印门装置中的硅胶缠绕

    公开(公告)号：US20080128767A1

    公开(公告)日：2008-06-05

    申请号：US11565801

    申请日：2006-12-01

    Applicant: James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    Inventor： James W. Adkisson ,  John J. Ellis-Monaghan ,  R. Michael Guidash ,  Mark D. Jaffe ,  Edward T. Nelson ,  Richard J. Rassel ,  Charles V. Stancampiano

    IPC: H01L27/146 ,  H01L31/18

    CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

    Abstract: A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.

    Abstract translation: 具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。 传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。 传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。 在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。 在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。 硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    89.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 有权
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07342268B2

    公开(公告)日：2008-03-11

    申请号：US10905277

    申请日：2004-12-23

    Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC: H01L31/062

    CPC classification number: H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    Abstract: An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    Abstract translation: 一种图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光敏度的像素阵列。 图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

Patent Agency Ranking