公开(公告)号：US20130168821A1

公开(公告)日：2013-07-04

申请号：US13343688

申请日：2012-01-04

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： H01L27/082 ,  H01L21/328 ,  H01L29/70

CPC分类号： H01L27/082 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735

摘要： A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

摘要翻译： 一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。 在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

公开(公告)号：US20120314485A1

公开(公告)日：2012-12-13

申请号：US13158420

申请日：2011-06-12

申请人： Jin Cai ,  Tak H. Ning

发明人： Jin Cai ,  Tak H. Ning

IPC分类号： G11C11/34 ,  H01L21/8222 ,  G11C11/00

CPC分类号： H01L27/082 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  H01L21/8228 ,  H01L21/84 ,  H01L27/1023 ,  H01L27/1203

摘要： An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

摘要翻译： 示例性实施例是包括SOI衬底的存储单元。 在SOI衬底上制造第一和第二组横向双极晶体管。 第一和第二组横向双极晶体管电耦合以形成两个反相器。 逆变器交叉耦合以形成存储元件。

公开(公告)号：US08314463B2

公开(公告)日：2012-11-20

申请号：US12542879

申请日：2009-08-18

申请人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

发明人： Jin Cai ,  Amlan Majumdar ,  Tak H. Ning ,  Zhibin Ren

IPC分类号： H01L27/12

CPC分类号： H01L29/1083 ,  H01L21/28052 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.

公开(公告)号：US20120256238A1

公开(公告)日：2012-10-11

申请号：US13080690

申请日：2011-04-06

申请人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/808 ,  H01L21/337

CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。 在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。 去除替代栅极结构以提供对半导体衬底的暴露部分的开口。 功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。 该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。

公开(公告)号：US20120235151A1

公开(公告)日：2012-09-20

申请号：US13048342

申请日：2011-03-15

申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried W. Haensch ,  Tak H. Ning

发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried W. Haensch ,  Tak H. Ning

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/737 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66265

摘要： A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

摘要翻译： 水平异质结双极晶体管（HBT）包括具有第一导电类型的掺杂的掺杂单晶Ge作为具有约0.66eV的能带隙的基极，以及掺杂有第二导电类型的掺杂多晶硅作为宽间隙 - 发射体具有约1.12eV的能带隙。 在一个实施例中，采用具有第二导电类型掺杂的掺杂多晶硅作为集电极。 在其它实施例中，采用具有第二导电类型掺杂的单晶Ge作为集电极。 在这样的实施例中，由于基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。 在两个实施例中，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。

公开(公告)号：US08217380B2

公开(公告)日：2012-07-10

申请号：US11971761

申请日：2008-01-09

申请人： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

发明人： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/148 ,  H01L27/0623 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.

摘要翻译： 具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。 存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。 此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。 在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。 间隔层包含在绝缘区域内。

公开(公告)号：US20110115553A1

公开(公告)日：2011-05-19

申请号：US12619285

申请日：2009-11-16

申请人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

发明人： Jin Cai ,  Robert H. Dennard ,  Ali Khakifirooz ,  Tak H. Ning ,  Jeng-Bang Yau

IPC分类号： G05F1/10 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7841

摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

摘要翻译： 提供具有至少一个可编程电浮动背板的SOI CMOS结构。 每个电浮动背板均可单独编程。 可以通过将电子注入每个导电浮动背板来进行编程。 编程的擦除可以通过将电子穿过浮动背板来实现。 两个装置中的至少一个可以完成电浮动背栅的编程。 这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。 使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

公开(公告)号：US20110115004A1

公开(公告)日：2011-05-19

申请号：US12618895

申请日：2009-11-16

申请人： Fadi H. Gebara ,  Tak H. Ning ,  Qiqing C. Ouyang ,  Jeremy D. Schaub

发明人： Fadi H. Gebara ,  Tak H. Ning ,  Qiqing C. Ouyang ,  Jeremy D. Schaub

IPC分类号： H01L27/146 ,  H01L31/0392 ,  H01L31/18

CPC分类号： H01L27/14634 ,  H01L21/743 ,  H01L23/481 ,  H01L27/1203 ,  H01L27/14636 ,  H01L27/14647 ,  H01L27/1469 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181

摘要： An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein.

摘要翻译： 提供了一种用于具有CMOS芯片和一个或多个薄化CMOS层的三维互补金属氧化物半导体（CMOS）堆叠芯片组件的嵌入式光电检测器装置。 一个或多个变薄的CMOS层中的至少一个包括限定在一个或多个变薄的CMOS层内的有源光电二极管区域，有源光电二极管区域接收入射到其上的光信号，并且有源光电二极管区域包括 减薄的CMOS层。 本体基板部分具有形成在其中的二极管光电检测器。

公开(公告)号：US07808039B2

公开(公告)日：2010-10-05

申请号：US12099879

申请日：2008-04-09

申请人： Jin Cai ,  Jeffrey B. Johnson ,  Tak H. Ning ,  Robert R. Robison

发明人： Jin Cai ,  Jeffrey B. Johnson ,  Tak H. Ning ,  Robert R. Robison

IPC分类号： H01L27/088

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/0722

摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.

摘要翻译： 绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。 源区具有第一导电类型。 体区具有第二导电类型并且位于源区和漏区之间。 源极横向双极晶体管包括基极，集电极和发射极。 硅化物区将基底连接到收集器。 发射器是身体区域。 集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。

公开(公告)号：US20090173928A1

公开(公告)日：2009-07-09

申请号：US11971761

申请日：2008-01-09

申请人： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

发明人： Bipin Rajendran ,  Tak H. Ning ,  Chung H. Lam

IPC分类号： H01L45/00

CPC分类号： H01L45/148 ,  H01L27/0623 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.

摘要翻译： 具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。 存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。 此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。 在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。 间隔层包含在绝缘区域内。