公开(公告)号：US20180157589A1

公开(公告)日：2018-06-07

申请号：US15370734

申请日：2016-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Yasuko Eckert

IPC: G06F12/0815 ,  G06F12/084

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0824 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/507 ,  G06F2212/60 ,  G06F2212/621

Abstract: A distributed shared-memory system includes several nodes that each have one or more processor cores, caches, local main memory, and a directory. Each node further includes predictors that use historical memory access information to predict future coherence permission requirements and speculatively initiate coherence operations. In one embodiment, predictors are included at processor cores for monitoring a memory access stream (e.g., historical sequence of memory addresses referenced by a processor core) and predicting addresses of future accesses. In another embodiment, predictors are included at the directory of each node for monitoring memory access traffic and coherence-related activities for individual cache lines to predict future demands for particular cache lines. In other embodiments, predictors are included at both the processor cores and directory of each node. Predictions from the predictors are used to initiate coherence operations to speculatively request promotion or demotion of coherence permissions.

公开(公告)号：US20180074958A1

公开(公告)日：2018-03-15

申请号：US15264804

申请日：2016-09-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Michael Boyer

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F2212/283 ,  G06F2212/62 ,  G06F2212/621

Abstract: A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.

公开(公告)号：US20170344479A1

公开(公告)日：2017-11-30

申请号：US15169118

申请日：2016-05-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. Boyer ,  Nuwan Jayasena

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F12/0822 ,  G06F2212/1004 ,  G06F2212/1016 ,  G06F2212/1032

Abstract: A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data.

公开(公告)号：US09755964B2

公开(公告)日：2017-09-05

申请号：US14859844

申请日：2015-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski ,  Nuwan Jayasena ,  Gabriel H. Loh

IPC: H04L12/40 ,  H04L12/781 ,  H04L29/06 ,  H04L12/715 ,  H04L12/861

CPC classification number: H04L45/52 ,  H04L45/04 ,  H04L49/9057 ,  H04L69/08

Abstract: A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue for transmission. The device is configured to receive at a payload extractor, a packet protocol change command from the controller and to remove the encoded data and to re-encode the data to create a re-encoded data packet and placing the re-encoded data packet in the second queue for transmission.

公开(公告)号：US20160086654A1

公开(公告)日：2016-03-24

申请号：US14492045

申请日：2014-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan Jayasena ,  Dong Ping Zhang

IPC: G11C11/4096 ,  G11C5/02 ,  G11C11/4078

CPC classification number: G11C11/4096 ,  G11C5/025 ,  G11C7/04 ,  G11C8/12

Abstract: A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.

Abstract translation: 管理存储器系统中的热水平的方法可以包括确定与存储器结构中的多个位置中的每一个相关联的预期热水平，以及针对存储器结构的多个操作的每个操作，将操作分配给 基于与操作相关联的热惩罚和与目标位置相关联的预期热水平，存储器结构中的多个物理位置的目标位置。

公开(公告)号：US20140181460A1

公开(公告)日：2014-06-26

申请号：US13723379

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lisa Hsu ,  Nuwan Jayasena ,  Andrew Kegel ,  Bradford M. Beckmann

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/302 ,  G06F2212/681 ,  G06F2212/684

Abstract: A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.

Abstract translation: 提供了一种数据处理设备，其采用与相应处理器相关联的多个翻译后备缓冲器（TLB），其配置为存储由处理器共享的存储器的页表的所选地址转换。 处理装置被配置为使得当处理器请求地址转换并且在与该处理器相关联的TLB中没有找到地址转换时，探测另一TLB用于请求的地址转换。 跨越其他TLB的探针可以在针对所请求的地址的页表的行进之前发生，或者可以与探针同时启动步行。 探头成功找到所请求的地址转换的地方，可以避免或停止页表的移动。

公开(公告)号：US20140177347A1

公开(公告)日：2014-06-26

申请号：US13721315

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niladrish Chatterjee ,  James O'Connor ,  Nuwan Jayasena ,  Gabriel Loh

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C2207/2236

Abstract: A method and apparatus for inter-row data transfer in memory devices is described. Data transfer from one physical location in a memory device to another is achieved without engaging the external input/output pins on the memory device. In an example method, a memory device is responsive to a row transfer (RT) command which includes a source row identifier and a target row identifier. The memory device activates a source row and storing source row data in a row buffer, latches the target row identifier into the memory device, activates a word line of a target row to prepare for a write operation, and stores the source row data from the row buffer into the target row.

Abstract translation: 描述了存储器件中行间数据传输的方法和装置。 从存储设备中的一个物理位置到另一物理位置的数据传输是在不将外部输入/输出引脚接入存储器件的情况下实现的。 在示例性方法中，存储器设备响应于包括源行标识符和目标行标识符的行传送（RT）命令。 存储器件激活源行并且将源行数据存储在行缓冲器中，将目标行标识符锁存到存储器件中，激活目标行的字线以准备写入操作，并存储源行数据 行缓冲区到目标行。

公开(公告)号：US12235756B2

公开(公告)日：2025-02-25

申请号：US17557568

申请日：2021-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Johnathan Alsop ,  Nuwan Jayasena

IPC: G06F12/06

Abstract: Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across multiple memory elements, such as DRAM banks, using bank-specific address information. In one implementation, the approach is used to process workloads with irregular updates to memory while consuming less command bus bandwidth than conventional approaches. Implementations include using conditional flags to selectively designate address information in local storage that is to be processed with the broadcast memory command.

公开(公告)号：US11934827B2

公开(公告)日：2024-03-19

申请号：US17556291

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC: G06F9/30 ,  G06F7/575 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F7/575 ,  G06F9/3001 ,  G06F9/3856

Abstract: An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

公开(公告)号：US11899642B2

公开(公告)日：2024-02-13

申请号：US16717027

申请日：2019-12-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena

IPC: G06F7/00 ,  G06F16/22 ,  G06F16/31

CPC classification number: G06F16/2255 ,  G06F16/328

Abstract: A method and apparatus perform a first hash operation on a first key wherein the first hash operation is biased to map the first key and associated value to a set of frequently-accessed buckets in a hash table. An entry for the first key and associated value is stored in the set of frequently-accessed buckets. A second hash operation is performed on a second key wherein the second hash operation is biased to map the second key and associated value to a set of less frequently-accessed buckets in the hash table. An entry for the second key and associated value is stored in the set of less frequently-accessed buckets. The method and apparatus perform a hash table look up of the requested key in the set of frequently-accessed buckets, if the requested key is not found, then a hash table lookup is performed in the set of less frequently-accessed buckets.