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144 条记录 (耗时 0.047 秒)

    Programmable transfer-devices
    82.
    发明授权
    Programmable transfer-devices 失效
    可编程传输设备

    公开(公告)号：US5247478A

    公开(公告)日：1993-09-21

    申请号：US846915

    申请日：1992-03-06

    申请人： Anil Gupta ,  Richard G. Cliff

    发明人： Anil Gupta ,  Richard G. Cliff

    IPC分类号： G11C7/10 ,  G11C16/04 ,  H03K17/693

    CPC分类号： G11C7/1006 ,  G11C16/0441 ,  H03K17/693

    摘要： A programmable, non-volatile transfer-device includes floating gate structures to control the transfer of signals from a set of inputs to a single output. Each floating gate structure includes two gates, logically coupled to each other in a master/slave mode, whereby the programming of the first gate controls the operation of the second gate. The floating gate structures are combined to implement a programmable multiplexer, without the use of static-RAM cells.

    摘要翻译： 可编程的非易失性转移装置包括浮动栅结构以控制从一组输入到单个输出的信号传输。 每个浮动栅极结构包括两个门，逻辑上以主/从模式彼此耦合，由此第一栅极的编程控制第二栅极的操作。 浮动栅极结构被组合以实现可编程多路复用器，而不使用静态RAM单元。

    Phase-locked loop architecture and clock distribution system
    84.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US08228102B1

    公开(公告)日：2012-07-24

    申请号：US12717062

    申请日：2010-03-03

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff ,  Tim Tri Hoang ,  Weiqi Ding ,  Sriram Narayan ,  Thungoc M. Tran ,  Kumara Tharmalingam

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    摘要： One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，该集成电路包括集成电路的第一侧上的第一条锁相环（PLL）电路，以及集成电路的第二侧的第二条PLL电路，该第二条与第一条 侧。 可以通过对集成电路进行编程来配置第一和第二条带中的PLL电路。 另一实施例涉及包括多个锁相环（PLL）电路和与多个PLL电路相邻的多个物理介质连接（PMA）三元组模块的集成电路。 每个PMA三元组模块包括第一，第二和第三通道。 第一和第三通道被布置为用作接收通道，并且第二通道被布置为可配置为接收通道或时钟倍增单元。 还公开了其它实施例和特征。

    Reducing false positives in configuration error detection for programmable devices
    85.
    发明授权
    Reducing false positives in configuration error detection for programmable devices 有权
    减少可编程器件配置错误检测中的误报

    公开(公告)号：US07620876B2

    公开(公告)日：2009-11-17

    申请号：US11407519

    申请日：2006-04-19

    申请人： David Lewis ,  Robert Blake ,  Richard G. Cliff ,  Srinivas T. Reddy

    发明人： David Lewis ,  Robert Blake ,  Richard G. Cliff ,  Srinivas T. Reddy

    IPC分类号： G11C29/00

    CPC分类号： G11C29/42 ,  G06F11/1008 ,  G11C29/52

    摘要： A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.

    摘要翻译： 设备通过使用掩蔽单元和灵敏度掩码数据来减少假阳性存储器错误检测，以从错误检测计算中排除存储器的未使用部分。 一种设备包括一个错误检测单元，用于从存储器读取数据并验证数据完整性。 灵敏度掩码数据指示存储器的未使用部分。 存储器的未使用部分可以对应于可编程设备的未使用部分的配置数据。 灵敏度掩码数据的每一位可以指示来自存储器的数据的一位或多位的使用。 响应于掩模数据，掩蔽单元将来自存储器的未使用部分的数据设置为不改变错误检测计算结果的值。 这防止来自存储器的未使用部分的数据中的任何错误引起错误信号。

    Tristate structures for programmable logic devices
    87.
    发明授权
    Tristate structures for programmable logic devices 失效
    可编程逻辑器件的三态结构

    公开(公告)号：US06882177B1

    公开(公告)日：2005-04-19

    申请号：US09832685

    申请日：2001-04-10

    申请人： Srinivas Reddy ,  Richard G. Cliff

    发明人： Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736

    摘要： A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

    摘要翻译： 包括三态结构的可编程逻辑器件架构。 可编程逻辑器件架构提供了可逻辑地或可编程地控制的三态结构，或两者。 通过这些三态结构，逻辑元件可以耦合到可编程互连，其中它们可以与可编程逻辑器件的其它逻辑元件耦合。 使用这些三态结构，可以动态地重新配置架构的信号路径。

    Phase-locked loop circuitry for programmable logic devices
    89.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06469553B1

    公开(公告)日：2002-10-22

    申请号：US09811946

    申请日：2001-03-19

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L700

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。