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292 条记录 (耗时 0.049 秒)

    Multi-mode synchronous memory device and methods of operating and testing same
    81.
    发明授权
    Multi-mode synchronous memory device and methods of operating and testing same 失效
    多模同步存储器件及其操作和测试方法相同

    公开(公告)号：US07057967B2

    公开(公告)日：2006-06-06

    申请号：US11001231

    申请日：2004-12-01

    申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

    IPC分类号： G11C8/00

    CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

    摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

    摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

    Vertically-adjustable mobile computer workstation and method of using same
    84.
    发明申请
    Vertically-adjustable mobile computer workstation and method of using same 审中-公开
    垂直可调移动电脑工作站及其使用方法

    公开(公告)号：US20060054751A1

    公开(公告)日：2006-03-16

    申请号：US10941231

    申请日：2004-09-15

    申请人： Brian Johnson ,  Gary Coonan

    发明人： Brian Johnson ,  Gary Coonan

    IPC分类号： A47F5/00

    CPC分类号： F16M11/24 ,  A47B9/00 ,  F16M11/2021 ,  F16M11/2092 ,  F16M11/38 ,  F16M11/42 ,  F16M13/00 ,  F16M2200/024 ,  F16M2200/044 ,  F16M2200/063

    摘要： Mobile computer workstations must be sufficiently large in order to be stable, but small enough to be easily maneuverable through a work place. A vertically-adjustable mobile computer workstation of the present disclosure includes a pole rotatably attached to a base supported by a plurality of rotatable members. The pole includes a first arm rotatably attached to a second arm. A computer support is attached to the second arm and is moveable between a sitting user position and a standing user position, at least in part, by pivoting the arms of the pole with respect to one another and the moveable base.

    摘要翻译： 移动计算机工作站必须足够大以便稳定，但足够小以便通过工作场所容易操纵。 本公开的可垂直调节的移动计算机工作站包括可旋转地附接到由多个可旋转构件支撑的基座的杆。 杆包括可旋转地附接到第二臂的第一臂。 计算机支撑件附接到第二臂，并且可以在坐使用者位置和站立的使用者位置之间移动，至少部分地通过相对于彼此和可移动的基座枢转杆的臂。

    Point of sale terminal having integrated customer and operator interfaces
    85.
    发明申请
    Point of sale terminal having integrated customer and operator interfaces 审中-公开
    销售点终端具有集成的客户和操作员界面

    公开(公告)号：US20050263590A1

    公开(公告)日：2005-12-01

    申请号：US11049921

    申请日：2005-02-03

    申请人： James Branck ,  Brian Johnson

    发明人： James Branck ,  Brian Johnson

    IPC分类号： G06K15/00 ,  G07G1/00

    CPC分类号： G07G1/0018

    摘要： The present invention provides an integrated point of sale transaction terminal that includes both operator and customer interfaces. A housing for the electronics of the point of sale terminal comprises an operator interface unit integrally associated therewith and extending from one side thereof and a customer interface unit integrally associated therewith and extending from the opposing side thereof.

    摘要翻译： 本发明提供了包括操作者和客户界面的综合销售点交易终端。 用于销售点终端的电子设备的壳体包括与其一体地相关联并从其一侧延伸的操作者接口单元和与其整体相关联并从其相对侧延伸的顾客接口单元。

    Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter
    87.
    发明授权
    Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter 有权
    使用双增量灰度代码计数器的先进先出存储器的移位寄存器实现

    公开(公告)号：US06857043B1

    公开(公告)日：2005-02-15

    申请号：US09761609

    申请日：2001-01-16

    申请人： Andy L. Lee ,  Brian Johnson ,  Richard G. Cliff

    发明人： Andy L. Lee ,  Brian Johnson ,  Richard G. Cliff

    IPC分类号： G06F5/10 ,  G06F5/14 ,  G06F12/00

    CPC分类号： G06F5/14 ,  G06F2205/102

    摘要： First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.

    摘要翻译： 先进先出（“FIFO”）存储器电路包括用于分别计数写入和读取时钟信号的第一和第二基于格雷码的计数器。 格雷码减法器从计数器输出的计数相减。 移位寄存器电路与写时钟信号同步地移位连续的数据字。 移位寄存器电路包括选择电路，其被配置为基于来自减法器的信息的格雷码解码来选择数据字之一。 也可以包括电路以监视来自减法器的信息以检测移位寄存器电路的全部或空的条件。

    Multilayered phase change memory
    88.
    发明申请
    Multilayered phase change memory 有权
    多层相变存储器

    公开(公告)号：US20050030800A1

    公开(公告)日：2005-02-10

    申请号：US10634130

    申请日：2003-08-04

    申请人： Brian Johnson ,  Stephen Hudgens

    发明人： Brian Johnson ,  Stephen Hudgens

    IPC分类号： G11C16/02 ,  H01L45/00 ,  G11C29/00

    CPC分类号： G11C13/0004 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/144

    摘要： A phase change layer may switch between more and less conductive states in response to electrical stimulation. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and an insulating barrier. The phase change layer may be positioned over a non-switching ovonic material which acts as an electrode, a resistive heater, and a thermal barrier.

    摘要翻译： 响应于电刺激，相变层可以在越来越少的导电状态之间切换。 相变层可以位于用作电极，电阻加热器和绝缘屏障的非开关式超声波材料上。 相变层可以位于作为电极，电阻加热器和热障壁的非切换式超声波材料上。

    Method and system for delay control in synchronization circuits
    90.
    发明授权
    Method and system for delay control in synchronization circuits 失效
    同步电路延时控制方法与系统

    公开(公告)号：US06836166B2

    公开(公告)日：2004-12-28

    申请号：US10339752

    申请日：2003-01-08

    申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson

    发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson

    IPC分类号： H03L706

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    摘要： A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.

    摘要翻译： 同步电路包括第一和第二移相路径电路，每个产生响应于输入信号的相移信号，并且相移信号相对于输入信号具有相应的精细和粗略的相移。 每个移相路径电路响应于控制信号调整粗略和精细的相移。 选择电路响应于选择信号输出一个相移信号。 控制电路监视输入信号和输出相移信号之间的相移，并产生选择和控制信号以选择一个相移路径电路并调整所选路径电路的精细相移和精细 和另一路径电路的粗相移。 当所选择的移相路径电路的精细延迟具有阈值时，控制电路产生选择信号以选择另一个移相电路。