公开(公告)号：US07355920B2

公开(公告)日：2008-04-08

申请号：US11355802

申请日：2006-02-16

申请人： James Brian Johnson ,  Feng Lin ,  Brent Keeth

发明人： James Brian Johnson ,  Feng Lin ,  Brent Keeth

IPC分类号： G11C8/00

CPC分类号： G11C29/50 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.

摘要翻译： 公开了一种用于在SDRAM中改进写延迟跟踪的方法和电路。 在一个实施例中，在写入路径的命令部分中使用延迟锁定环，并且接收系统时钟作为其参考输入。 DLL包括建模延迟，其将内部写入有效信号的传输延迟和系统时钟分布建模到写入路径的数据路径部分中的解串行器，否则由间歇性断言的写入选通信号控制。 随着系统时钟（Clk）的输入分配延迟和设计匹配的写选通（WS），分布式系统时钟和写有效信号通过参考系统时钟的DLL延迟与WS分配路径同步 输入到DLL。 通过将分发延迟从发送到解串器的系统时钟中提取出来，写入有效信号与写入选通有效地同步，其影响是数据将及时从解串器电路传送到存储器阵列，并与 编程写延迟。

公开(公告)号：US07251194B2

公开(公告)日：2007-07-31

申请号：US11352078

申请日：2006-02-10

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C8/18

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

摘要翻译： 存储器系统将命令，地址或写入数据信号从存储器控制器耦合到存储器件，并将数据信号从存储器件读取到存储器控制器。 每个存储器控制器和存储器件中的相应选通发生器电路都产生同相选通信号和正交选通信号。 存储在存储器控制器中的相应输出锁存器中的命令，地址或写入数据信号由来自内部选通发生器电路的同相信号计时。 这些命令，地址或写入数据信号通过从存储器控制器耦合到存储器件的正交选通信号而被锁存在存储器件中的输入锁存器中。 以基本相同的方式，使用由内部选通发生器电路产生的同相和正交选通信号，将读取的数据信号从存储器件耦合到存储器控制器。

公开(公告)号：US07126874B2

公开(公告)日：2006-10-24

申请号：US10931472

申请日：2004-08-31

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C8/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

摘要翻译： 存储器系统将命令，地址或写入数据信号从存储器控制器耦合到存储器件，并将数据信号从存储器件读取到存储器控制器。 每个存储器控制器和存储器件中的相应选通发生器电路都产生同相选通信号和正交选通信号。 存储在存储器控制器中的相应输出锁存器中的命令，地址或写入数据信号由来自内部选通发生器电路的同相信号计时。 这些命令，地址或写入数据信号通过从存储器控制器耦合到存储器件的正交选通信号而被锁存在存储器件中的输入锁存器中。 以基本相同的方式，使用由内部选通发生器电路产生的同相和正交选通信号，将读取的数据信号从存储器件耦合到存储器控制器。

公开(公告)号：US20060140023A1

公开(公告)日：2006-06-29

申请号：US11352078

申请日：2006-02-10

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US20060133165A1

公开(公告)日：2006-06-22

申请号：US11351836

申请日：2006-02-10

申请人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

发明人： Feng Lin ,  Brent Keeth ,  Brian Johnson ,  Seong-hoon Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222

摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.

公开(公告)号：US07031215B2

公开(公告)日：2006-04-18

申请号：US11031437

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C11/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06909196B2

公开(公告)日：2005-06-21

申请号：US10178172

申请日：2002-06-21

申请人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

发明人： Shubneesh Batra ,  Michael D. Chaine ,  Brent Keeth ,  Salman Akram ,  Troy A. Manning ,  Brian Johnson ,  Chris G. Martin ,  Todd A. Merritt ,  Eric J. Smith

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L23/5222 ,  H01L24/03 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at least partially exposed at the top surface of the integrated circuit, forming a metal pad on the metal level below the bond pad and forming an underlying metal pad on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads to the area of the bond pad is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.

摘要翻译： 描述了一种降低具有三个或更多个金属水平的集成电路中的寄生电容的方法。 该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘，在接合焊盘下方的金属层上形成金属焊盘，并在一个或多个下金属层的每一个上形成下面的金属焊盘。 在所示的实施例中，下面的金属焊盘中的至少一个的面积与焊盘的面积之比小于30％。 寄生电容因此大大降低，信号传播速度提高。

公开(公告)号：US06876562B2

公开(公告)日：2005-04-05

申请号：US10273869

申请日：2002-10-17

申请人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

发明人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C5/06

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US06678205B2

公开(公告)日：2004-01-13

申请号：US10036141

申请日：2001-12-26

申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

IPC分类号： G11C800

CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal, control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端，并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号，该设备中的控制电路响应于 施加到设备的异步输入终端的预定的异步信号序列，以将设备置于其中禁用内部时钟电路的替代操作模式，使得可以使用具有频率的外部时钟信号在替代模式下操作该设备 小于预定的最小频率。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

公开(公告)号：US06445643B2

公开(公告)日：2002-09-03

申请号：US09745608

申请日：2000-12-20

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

摘要： A method of setting write latency and a write/valid indicator circuit for use with the method. In a preferred embodiment, time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. The write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

摘要翻译： 设置写延迟的方法和用于该方法的写/有效指示器电路。 在优选实施例中，时间裕度区域刚好在第一或前沿之后并且刚好在时钟信号的前导码的第二或后续边缘之前建立，使得等待时间设置将被发现是不可接受的，如果它使得写使能信号转变 在这两个地区。 写入/有效指示电路通过延迟时钟信号或写入使能信号并将它们的定时与未延时写入使能信号或时钟信号的定时进行比较来创建起始和结束时间裕度区域。