利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

195 条记录 (耗时 0.045 秒)

    Integrated circuit line with electromigration barriers
    81.
    发明授权
    Integrated circuit line with electromigration barriers 失效
    集成电路线与电迁移障碍

    公开(公告)号：US08211776B2

    公开(公告)日：2012-07-03

    申请号：US12652485

    申请日：2010-01-05

    申请人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

    发明人： David V. Horak ,  Takeshi Nogami ,  Shom Ponoth ,  Chih-Chao Yang

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating an integrated circuit comprising an electromigration barrier in a line of the integrated circuit includes forming a spacer; forming a segmented line adjacent to opposing sides of the spacer, the segmented line formed from a first conductive material; removing the spacer to form an empty line break; and filling the empty line break with a second conductive material to form an electromigration barrier that isolates electromigration effects within individual segments of the segmented line. An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.

    摘要翻译： 一种用于制造集成电路的集成电路的方法，包括：集成电路的一行中的电迁移势垒包括形成间隔物; 形成与所述间隔物的相对侧相邻的分段线，所述分段线由第一导电材料形成; 移除间隔物以形成空线断裂; 并用第二导电材料填充空线断裂以形成电隔离屏蔽，其隔离分段线的各个段内的电迁移效应。 包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料 线路各部分的电迁移效应。

    PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER
    82.
    发明申请
    PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER 失效
    DLC介电层可编程防结构

    公开(公告)号：US20110018093A1

    公开(公告)日：2011-01-27

    申请号：US12509892

    申请日：2009-07-27

    申请人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

    发明人： Chih-Chao Yang ,  David V. Horak ,  Takeshi Nogami ,  Shom Ponoth

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5252 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein.

    摘要翻译： 在一个实施例中，提供了一种抗熔丝结构，其包括具有至少第一抗熔融区域和第二抗熔融区域的第一电介质材料，其中至少一个反熔丝区域包括嵌入在该熔断区域内的导电区域 第一电介质材料。 反熔丝结构还包括第一金刚石碳层，其具有位于第一抗熔融区域中的至少第一电介质材料上的第一导电性，第二类金刚石碳层具有位于至少第一电介质上的第二导电性 材料在第二个反熔丝区域。 在本实施例中，第二导电率不同于第一导电性，第一类金刚石碳层和第二类金刚石碳层具有相同的厚度。 反熔丝结构还包括位于第一和第二金刚石状碳层顶上的第二电介质材料。 第二电介质材料包括嵌入其中的至少一个导电填充区域。

    INTERCONNECT STRUCTURE
    83.
    发明申请
    INTERCONNECT STRUCTURE 有权
    互连结构

    公开(公告)号：US20100264543A1

    公开(公告)日：2010-10-21

    申请号：US12424843

    申请日：2009-04-16

    申请人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    发明人： Shom Ponoth ,  David V. Horak ,  Takeshi Nogami ,  Chih-Chao Yang

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76847 ,  H01L21/76805 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.

    摘要翻译： 公开了用于形成半导体互连结构的互连结构和方法。 在一个实施例中，互连结构包括：衬底，其包括第一衬里层和其上的第一金属层; 在所述第一金属层和所述衬底上的介电阻挡层; 电介质阻挡层上的层间电介质层; 所述通孔在所述层间电介质层，所述电介质阻挡层和所述第一金属层之间延伸，所述通孔在其上包括第二衬垫层和第二金属层; 以及位于所述第二衬垫层和所述第一金属层之间的扩散阻挡层，其中所述扩散阻挡层的一部分位于所述电介质阻挡层下方。

    Method of making a semiconductor structure with a plating enhancement layer
    84.
    发明授权
    Method of making a semiconductor structure with a plating enhancement layer 有权
    制造具有电镀增强层的半导体结构的方法

    公开(公告)号：US07341948B2

    公开(公告)日：2008-03-11

    申请号：US11306930

    申请日：2006-01-17

    申请人： Shom Ponoth ,  Steven Shyng-Tsong Chen ,  John Anthony Fitzsimmons ,  Terry Allen Spooner

    发明人： Shom Ponoth ,  Steven Shyng-Tsong Chen ,  John Anthony Fitzsimmons ,  Terry Allen Spooner

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76873 ,  H01L21/7688 ,  H01L2221/1089

    摘要： Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.

    摘要翻译： 公开了一种半导体结构的制造方法，其特征在于，在半导体层上形成层间电介质层（ILD）层，在ILD上形成导电性电镀增强层（PEL），图案化ILD和PEL， 进入由ILD和PEL形成的图案，然后在种子层上镀铜。 PEL用于降低晶片上的电阻，以便于镀铜。 PEL优选是光学透明且导电的层。

    GCIB LINER AND HARDMASK REMOVAL PROCESS
    85.
    发明申请
    GCIB LINER AND HARDMASK REMOVAL PROCESS 有权
    GCIB LINER和HARDMASK拆卸过程

    公开(公告)号：US20070117342A1

    公开(公告)日：2007-05-24

    申请号：US11164423

    申请日：2005-11-22

    申请人： Shyng-Tsong Chen ,  John Fitzsimmons ,  Shom Ponoth ,  Terry Spooner

    发明人： Shyng-Tsong Chen ,  John Fitzsimmons ,  Shom Ponoth ,  Terry Spooner

    IPC分类号： H01L21/76

    CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7684

    摘要： A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.

    摘要翻译： 一种方法包括在衬底上沉积电介质膜层，硬掩模层和图案化光刻胶层。 该方法还包括通过反应离子蚀刻处理选择性地蚀刻电介质膜层以形成亚光刻特征，并沉积阻挡金属层和铜层。 该方法还包括通过气体簇离子束（GCIB）处理蚀刻阻挡金属层和硬掩模层。

    DENSIFYING SURFACE OF POROUS DIELECTRIC LAYER USING GAS CLUSTER ION BEAM
    86.
    发明申请
    DENSIFYING SURFACE OF POROUS DIELECTRIC LAYER USING GAS CLUSTER ION BEAM 审中-公开
    使用气体离子束对多孔介质层的表面进行测量

    公开(公告)号：US20080090402A1

    公开(公告)日：2008-04-17

    申请号：US11536893

    申请日：2006-09-29

    申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

    发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76825 ,  H01J2237/0812 ,  H01L21/76883

    摘要： A method of fabricating and a structure of an integrated circuit (IC) incorporating a porous dielectric layer are disclosed. A metal line is formed in the porous dielectric layer. A gas cluster ion beam process is applied to the porous dielectric layer so that an upper portion of the dielectric layer is densified to be not porous or non-interconnected low porous, while a lower portion of the porous dielectric layer still maintains its ultra-low dielectric constant after the gas cluster ion beam process.

    摘要翻译： 公开了一种制造方法和结合有多孔介电层的集成电路（IC）的结构。 在多孔介电层中形成金属线。 将气体簇离子束工艺应用于多孔介电层，使得电介质层的上部被致密化为不是多孔的或不互连的低多孔，而多孔介电层的下部仍保持其超低 气体离子束过程后的介电常数。

    MAINTAINING UNIFORM CMP HARD MASK THICKNESS
    87.
    发明申请
    MAINTAINING UNIFORM CMP HARD MASK THICKNESS 有权
    维持均匀的CMP硬掩模厚度

    公开(公告)号：US20060043590A1

    公开(公告)日：2006-03-02

    申请号：US10711145

    申请日：2004-08-27

    申请人： Steven Shyng-Tsong Chen ,  Kaushik Kumar ,  Stephen Greco ,  Shom Ponoth ,  Terry Spooner ,  David Rath ,  Wei-Tsu Tseng

    发明人： Steven Shyng-Tsong Chen ,  Kaushik Kumar ,  Stephen Greco ,  Shom Ponoth ,  Terry Spooner ,  David Rath ,  Wei-Tsu Tseng

    IPC分类号： H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

    摘要翻译： 化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。 使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。 使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。 以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。