公开(公告)号：US09330933B2

公开(公告)日：2016-05-03

申请号：US12137259

申请日：2008-06-11

Applicant: Burn Jeng Lin

Inventor： Burn Jeng Lin

IPC: B29C59/02 ,  H01L21/3105 ,  H01L21/67

CPC classification number: H01L21/67092 ,  H01L21/31051 ,  H01L21/31058

Abstract: A method for planarizing a polymer layer is provided which includes providing a substrate having the polymer layer formed thereon, providing a structure having a substantially flat surface, pressing the flat surface of the structure to a top surface of the polymer layer such that the top surface of the polymer layer substantially conforms to the flat surface of the structure, and separating the flat surface of the structure from the top surface of the polymer material layer.

Abstract translation: 提供了一种用于平面化聚合物层的方法，其包括提供其上形成有聚合物层的基底，提供具有基本平坦表面的结构，将该结构的平坦表面压在聚合物层的顶表面上，使得顶表面 的聚合物层基本上符合结构的平坦表面，并且将结构的平坦表面与聚合物材料层的顶表面分离。

公开(公告)号：US09182660B2

公开(公告)日：2015-11-10

申请号：US13486000

申请日：2012-06-01

Applicant: Wen-Chuan Wang ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Burn Jeng Lin

Inventor： Wen-Chuan Wang ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Burn Jeng Lin

IPC: G03F1/56 ,  G03F1/78 ,  H01L21/027 ,  G03F7/20

CPC classification number: G03F1/56 ,  G03F1/78 ,  G03F7/2063 ,  H01L21/0276 ,  H01L21/0277

Abstract: A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process.

Abstract translation: 电子束图案化方法包括在基板上形成导电材料层; 在导电材料层上形成底部抗反射涂层（BARC）层; 在BARC层上形成抗蚀剂层; 并将电子束（电子束）引导到用于电子束图案化工艺的敏感抗蚀剂层。 BARC层被设计成使得在电子束图案化工艺期间抗蚀剂层的顶部电势基本为零。

公开(公告)号：US08762900B2

公开(公告)日：2014-06-24

申请号：US13534765

申请日：2012-06-27

Applicant: Jaw-Jung Shin ,  Shy-Jay Lin ,  Hua-Tai Lin ,  Burn Jeng Lin

Inventor： Jaw-Jung Shin ,  Shy-Jay Lin ,  Hua-Tai Lin ,  Burn Jeng Lin

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.

Abstract translation: 集成电路（IC）设计的方法包括接收IC设计布局。 IC设计布局包括具有第一外边界的IC特征和分配给第一外边界的第一目标点。 该方法还包括为IC特征产生第二外部边界并将所有第一目标点移动到第二外部边界以形成修改的IC设计布局。

公开(公告)号：US08722286B2

公开(公告)日：2014-05-13

申请号：US13484588

申请日：2012-05-31

Applicant: Chen-Hua Yu ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Burn Jeng Lin

Inventor： Chen-Hua Yu ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Burn Jeng Lin

IPC: G03F1/20

CPC classification number: G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/045 ,  H01J37/3175 ,  H01J37/3177 ,  H01J2237/31774 ,  H01J2237/31789 ,  Y10S430/143

Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.

Abstract translation: 对反射型电子束光刻装置及其制造方法进行说明。 该装置包括基板，形成在基板上的多个导电层，它们彼此平行并由绝缘柱结构分隔开，并且在每个导电层中形成多个孔。 每个导电层中的孔与其它导电层中的孔垂直对准，并且每个孔的周边包括悬浮的导电层。

公开(公告)号：US20140007023A1

公开(公告)日：2014-01-02

申请号：US13534765

申请日：2012-06-27

Applicant: Jaw-Jung Shin ,  Shy-Jay Lin ,  Hua-Tai Lin ,  Burn Jeng Lin

Inventor： Jaw-Jung Shin ,  Shy-Jay Lin ,  Hua-Tai Lin ,  Burn Jeng Lin

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.

Abstract translation: 集成电路（IC）设计的方法包括接收IC设计布局。 IC设计布局包括具有第一外边界的IC特征和分配给第一外边界的第一目标点。 该方法还包括为IC特征产生第二外部边界并将所有第一目标点移动到第二外部边界以形成修改的IC设计布局。

公开(公告)号：US20130323918A1

公开(公告)日：2013-12-05

申请号：US13486000

申请日：2012-06-01

Applicant: Wen-Chuan Wang ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Burn Jeng Lin

Inventor： Wen-Chuan Wang ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Burn Jeng Lin

IPC: H01L21/02

CPC classification number: G03F1/56 ,  G03F1/78 ,  G03F7/2063 ,  H01L21/0276 ,  H01L21/0277

Abstract: A method for electron-beam patterning includes forming a conductive material layer on a substrate; forming a bottom anti-reflective coating (BARC) layer on the conductive material layer; forming a resist layer on the BARC layer; and directing an electron beam (e-beam) to the sensitive resist layer for an electron beam patterning process. The BARC layer is designed such that a top electrical potential of the resist layer is substantially zero during the e-beam patterning process.

Abstract translation: 电子束图案化方法包括在基板上形成导电材料层; 在导电材料层上形成底部抗反射涂层（BARC）层; 在BARC层上形成抗蚀剂层; 并将电子束（电子束）引导到用于电子束图案化工艺的敏感抗蚀剂层。 BARC层被设计成使得在电子束图案化工艺期间抗蚀剂层的顶部电势基本为零。

公开(公告)号：US20130320225A1

公开(公告)日：2013-12-05

申请号：US13484588

申请日：2012-05-31

Applicant: Chen-Hua Yu ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Burn Jeng Lin

Inventor： Chen-Hua Yu ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Burn Jeng Lin

IPC: H01J3/16 ,  B05D5/12

CPC classification number: G03F1/20 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/045 ,  H01J37/3175 ,  H01J37/3177 ,  H01J2237/31774 ,  H01J2237/31789 ,  Y10S430/143

Abstract: A device for reflective electron-beam lithography and methods of producing the same are described. The device includes a substrate, a plurality of conductive layers formed on the substrate, which are parallel to each other and separated by insulating pillar structures, and a plurality of apertures in each conductive layer. Apertures in each conductive layer are vertically aligned with the apertures in other conductive layers and a periphery of each aperture includes conductive layers that are suspended.

Abstract translation: 对反射型电子束光刻装置及其制造方法进行说明。 该装置包括基板，形成在基板上的多个导电层，它们彼此平行并由绝缘柱结构分隔开，并且在每个导电层中形成多个孔。 每个导电层中的孔与其它导电层中的孔垂直对准，并且每个孔的周边包括悬浮的导电层。

公开(公告)号：US08584057B2

公开(公告)日：2013-11-12

申请号：US13409653

申请日：2012-03-01

Applicant: Pei-Yi Liu ,  Shy-Jay Lin ,  Wen-Chuan Wang ,  Jaw-Jung Shin ,  Burn Jeng Lin

Inventor： Pei-Yi Liu ,  Shy-Jay Lin ,  Wen-Chuan Wang ,  Jaw-Jung Shin ,  Burn Jeng Lin

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC classification number: G03F7/00 ,  G03F1/00 ,  G03F7/70433 ,  G06F17/5081 ,  G06F19/00 ,  G21K5/00

Abstract: A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid.

Abstract translation: 描述了光刻工艺中数据准备的方法。 该方法包括在图形数据库系统（GDS）网格中提供集成电路（IC）布局设计，将IC布局设计GDS网格转换为第一曝光网格，将非定向抖动技术应用于第一曝光，与应用 将第一曝光栅格抖动到第一曝光栅格，将栅格移位施加到第一曝光栅格以产生栅格移动的曝光栅格并向栅格曝光栅格施加抖动，并将第一曝光栅格（在接收抖动之后）添加到栅格 转换曝光网格（在接收到抖动之后）以产生第二曝光网格。

公开(公告)号：US08563198B2

公开(公告)日：2013-10-22

申请号：US13160231

申请日：2011-06-14

Applicant: Burn Jeng Lin ,  Jeng Horng Chen ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Jen-Chieh Shih

Inventor： Burn Jeng Lin ,  Jeng Horng Chen ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Jen-Chieh Shih

IPC: G03F1/46 ,  G03F1/48

CPC classification number: G03F1/50 ,  G03F1/46

Abstract: Disclosed is a photomask having a wavelength-reducing material that may be used during photolithographic processing. In one example, the photomask includes a transparent substrate, an absorption layer having at least one opening, and a layer of wavelength-reducing material (WRM) placed into the opening. The thickness of the WRM may range from approximately a thickness of the absorption layer to approximately ten times the wavelength of light used during the photolithographic processing. In another example, the photomask includes at least one antireflection coating (ARC) layer.

Abstract translation: 公开了一种光掩模，其具有在光刻处理期间可以使用的波长减小材料。 在一个示例中，光掩模包括透明基板，具有至少一个开口的吸收层和放置在开口中的波长减小材料层（WRM）。 WRM的厚度可以在大约从吸收层的厚度到在光刻处理期间使用的光的波长的大约十倍的范围内。 在另一示例中，光掩模包括至少一个抗反射涂层（ARC）层。

公开(公告)号：US20130203001A1

公开(公告)日：2013-08-08

申请号：US13368877

申请日：2012-02-08

Applicant: Wen-Chuan Wang ,  Shy-Jay Lin ,  Pei-Yi Liu ,  Jaw-Jung Shin ,  Burn Jeng Lin

Inventor： Wen-Chuan Wang ,  Shy-Jay Lin ,  Pei-Yi Liu ,  Jaw-Jung Shin ,  Burn Jeng Lin

IPC: G03F7/20

CPC classification number: G03F7/2022 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/20 ,  G03F7/704 ,  H01J37/3026 ,  H01J37/3174 ,  Y10S430/143

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (Δt) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

Abstract translation: 公开了一种制造半导体器件的方法。 一种示例性方法包括接收包括网格上的目标图案的集成电路（IC）布局设计。 该方法还包括接收多网格结构。 多栅格结构包括多个曝光网格段，其在第一方向上彼此偏移一个偏移量。 该方法还包括执行多栅格曝光以将衬底上的目标图案曝光，从而在衬底上形成电路特征图案。 执行多栅格曝光包括在第二方向上以多栅格结构扫描衬底，使得暴露的目标图案的子像素偏移在第一方向上发生，并且使用增量时间（Deltat）使得子像素 曝光的目标图案的像素位移在第二方向发生。