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89 条记录 (耗时 0.037 秒)

    Semiconductor device with high-k gate dielectric
    82.
    发明授权
    Semiconductor device with high-k gate dielectric 有权
    具有高k栅极电介质的半导体器件

    公开(公告)号：US07045847B2

    公开(公告)日：2006-05-16

    申请号：US10832020

    申请日：2004-04-26

    申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

    发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

    IPC分类号： H01L27/108

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

    摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

    Inflected Magnetoresistive Structures, Memory Cells Having Inflected Magnetoresistive Structures, and Fabrication Methods
    83.
    发明申请
    Inflected Magnetoresistive Structures, Memory Cells Having Inflected Magnetoresistive Structures, and Fabrication Methods 失效
    反射磁阻结构，具有磁阻结构的记忆单元，以及制造方法

    公开(公告)号：US20060081952A1

    公开(公告)日：2006-04-20

    申请号：US11163118

    申请日：2005-10-05

    申请人： Chun-Chieh Lin

    发明人： Chun-Chieh Lin

    IPC分类号： H01L43/00

    CPC分类号： H01L27/228 ,  H01L43/08

    摘要： Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.

    摘要翻译： 本文公开了具有非平面形式的磁阻结构。 本发明的MR结构的实施例包括那些在MR结构的第一部分之间相对于衬底稍微垂直的第一部分和MR结构相对于衬底稍微水平的第二部分的至少一个拐点。 这种结构可以用于存储器件，例如MRAM存储器件，其中与具有先前的平面MR结构的器件相比，存储器密度增加而不减小MR结构的表面积。

    Method of forming DRAM capacitors with protected outside crown surface for more robust structures
    87.
    发明授权
    Method of forming DRAM capacitors with protected outside crown surface for more robust structures 有权
    形成具有受保护的外冠表面的DRAM电容器的方法用于更坚固的结构

    公开(公告)号：US06875655B2

    公开(公告)日：2005-04-05

    申请号：US10802564

    申请日：2004-03-17

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    Ultra-thin body transistor with recessed silicide contacts
    88.
    发明申请
    Ultra-thin body transistor with recessed silicide contacts 审中-公开
    具有凹陷硅化物触点的超薄体晶体管

    公开(公告)号：US20050045949A1

    公开(公告)日：2005-03-03

    申请号：US10650445

    申请日：2003-08-28

    申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

    发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/68 ,  H01L29/786

    CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/78618 ,  H01L29/78654

    摘要： A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

    摘要翻译： 一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210） （240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。 还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

    Method of forming a protected crown capacitor structure utilizing the outside crown surface to increase capacitance
    89.
    发明授权
    Method of forming a protected crown capacitor structure utilizing the outside crown surface to increase capacitance 有权
    使用外冠表面形成保护的冠状电容器结构以增加电容的方法

    公开(公告)号：US06656844B1

    公开(公告)日：2003-12-02

    申请号：US09981437

    申请日：2001-10-18

    申请人： Chun-Chieh Lin ,  Wong-Cheng Shih

    发明人： Chun-Chieh Lin ,  Wong-Cheng Shih

    IPC分类号： H01L21301

    CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

    摘要： A method of forming a DRAM capacitor structure featuring increased surface area, has been developed. The method features a polysilicon top plate structure located overlying an array comprised of individual polysilicon storage node structures. Each polysilicon storage node structure is comprised with tall, vertical features, and additional surface area is obtained via removal of butted insulator layer from a first group of surfaces of the storage node structures. Insulator layer remains butted to a second group of storage node structure surfaces to prevent collapse of the tall, vertical features of the storage node structures during subsequent processing sequences.

    摘要翻译： 已经开发了形成具有增加的表面积的DRAM电容器结构的方法。 该方法具有位于由单个多晶硅存储节点结构组成的阵列上方的多晶硅顶板结构。 每个多晶硅存储节点结构包括高垂直特征，并且通过从存储节点结构的第一组表面去除对接的绝缘体层来获得额外的表面积。 绝缘体层保持对接到第二组存储节点结构表面，以防止后续处理序列期间存储节点结构的高垂直特征的崩溃。