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    Redundant antifuse segments for improved programming efficiency
    81.
    发明授权
    Redundant antifuse segments for improved programming efficiency 有权
    冗余反熔丝段，以提高编程效率

    公开(公告)号：US06621324B2

    公开(公告)日：2003-09-16

    申请号：US09683808

    申请日：2002-02-19

    申请人： John A. Fifield ,  William R. Tonti

    发明人： John A. Fifield ,  William R. Tonti

    IPC分类号： H01H3776

    CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.

    摘要翻译： 公开了一种用于提高编程效率的反熔丝结构，其中反熔丝结构包括提供第一电压的第一节点，多个反熔丝元件和多个第一开关。 多个反熔丝元件通常连接到第一节点。 多个第一开关在编程模式期间被依次启动，以分别对每个反熔丝元件施加第一电压。 反熔丝结构可以包括提供第二电压的第二节点。 多个第一开关中的每一个可以耦合在第二节点和多个反熔丝元件中的对应的一个之间。 反熔丝结构还可以包括连接熔丝闩锁的第三节点。 多个第二开关可以耦合在第三节点和多个反熔丝元件中的对应的一个之间。 多个第二开关可以在读取模式期间同时被激活。

    SOI hybrid structure with selective epitaxial growth of silicon
    83.
    发明授权
    SOI hybrid structure with selective epitaxial growth of silicon 有权

    公开(公告)号：US06555891B1

    公开(公告)日：2003-04-29

    申请号：US09690674

    申请日：2000-10-17

    申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    IPC分类号： H01L2900

    CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

    摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

    Trench field shield in trench isolation
    85.
    发明授权
    Trench field shield in trench isolation 失效
    沟槽隔离屏蔽沟槽

    公开(公告)号：US06420749B1

    公开(公告)日：2002-07-16

    申请号：US09602427

    申请日：2000-06-23

    申请人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    发明人： Ramachandra Divakaruni ,  Jeffrey P. Gambino ,  Edward W. Kiewra ,  Jack A. Mandelman ,  Carl Radens ,  William R. Tonti

    IPC分类号： H01L27108

    CPC分类号： H01L21/823481 ,  H01L21/743 ,  H01L21/76232 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/10897

    摘要： A method and structure for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. A first conductive sidewall spacer is electrically connected to a first device of said plurality of devices and a second conductive sidewall spacer is electrically connected to a second device of the plurality of devices. The first device can be biased independently of the second device. A contact extends above a surface of the substrate. A first contact abuts a first device and a first conductive sidewall spacer. An insulator separates the conductive sidewall spacers. A first contact may be equidistant between the first conductor and the second conductor. The conductive sidewall spacers comprise field shields.

    摘要翻译： 一种用于半导体器件的方法和结构，其包括：衬底，其包括沟槽，在衬底上隔离的衬底上的多个器件，沟槽内的导电侧壁间隔物，以及填充导电侧壁间隔物之间​​的沟槽的绝缘体。 第一导电侧壁间隔件电连接到所述多个器件中的第一器件，并且第二导电侧壁间隔件电连接到多个器件中的第二器件。 第一装置可以独立于第二装置而被偏置。 接触件在衬底的表面上方延伸。 第一接触件邻接第一器件和第一导电侧壁间隔物。 绝缘体将导电侧墙隔离开。 第一接触件可以在第一导体和第二导体之间等距。 导电侧壁间隔件包括场屏蔽。

    Method of forming bitline diffusion halo under gate conductor ledge
    87.
    发明授权
    Method of forming bitline diffusion halo under gate conductor ledge 失效
    在栅极导体突起处形成位线扩散晕的方法

    公开(公告)号：US06274441B1

    公开(公告)日：2001-08-14

    申请号：US09560073

    申请日：2000-04-27

    申请人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  William R. Tonti

    发明人： Jack A. Mandelman ,  Ramachandra Divakaruni ,  William R. Tonti

    IPC分类号： H01L2170

    CPC分类号： H01L29/1045 ,  H01L21/266 ,  H01L27/10861 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66659

    摘要： A method for fabricating a MOSFET device including a halo implant comprising providing a semiconductor substrate, a gate insulator layer, a conductor layer, an overlying silicide layer, and an insulating cap; patterning and etching the silicide layer and the insulating cap; providing insulating spacers along sides of said silicide layer and insulating cap; implanting node and bitline N+ diffusion regions; patterning a photoresist layer to protect the node diffusion region and supporting PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; etching exposed spacer material from the side of said silicide layer and insulating cap; implanting a P-type impurity halo implant into the exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulating spacer along the exposed side of said silicide layer and insulating cap.

    摘要翻译： 一种制造包括卤素注入的MOSFET器件的方法，包括提供半导体衬底，栅极绝缘体层，导体层，上覆硅化物层和绝缘帽; 图案化和蚀刻硅化物层和绝缘帽; 在所述硅化物层和绝缘盖的侧面提供绝缘垫片; 植入节点和位线N +扩散区域; 图案化光致抗蚀剂层以保护节点扩散区域并支持PFET源极和漏极区域并暴露位线扩散区域和NFET源极和漏极区域; 从所述硅化物层和绝缘盖的侧面蚀刻暴露的间隔物材料; 将P型杂质卤素注入植入暴露的位线扩散区并支持NFET源极和漏极区; 并剥离光致抗蚀剂层，并沿着所述硅化物层和绝缘帽的暴露侧提供绝缘间隔物。

    Structures for wafer level test and burn-in
    88.
    发明授权
    Structures for wafer level test and burn-in 失效
    晶圆级测试和老化的结构

    公开(公告)号：US06233184B1

    公开(公告)日：2001-05-15

    申请号：US09191954

    申请日：1998-11-13

    申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

    IPC分类号： G11C2900

    CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

    摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

    摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

    Single-ended semiconductor receiver with built in threshold voltage difference
    89.
    发明授权
    Single-ended semiconductor receiver with built in threshold voltage difference 失效
    单端半导体接收器内置阈值电压差

    公开(公告)号：US06222395B1

    公开(公告)日：2001-04-24

    申请号：US09225112

    申请日：1999-01-04

    申请人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    发明人： Claude L. Bertin ,  Russell J. Houghton ,  William R. Tonti

    IPC分类号： G05F110

    CPC分类号： G05F3/205

    摘要： A differential receiver for sensing small input voltage swings by using a built in reference voltage obtained by a difference in threshold voltage between a differential pair of closely spaced transistors. The difference in threshold voltage can be produced by different values of ion implantation of the gates of the transistor pair with the same material, or by dosages using different materials. The difference in threshold voltage can also be obtained by using different transistor channel lengths. The threshold voltages can also be modulated by the control of the transistor substrate voltages using a voltage control substrate means.

    摘要翻译： 一种差分接收器，用于通过使用通过差分对间隔晶体管之间的阈值电压差而获得的内置参考电压来感测小输入电压摆幅。 阈值电压的差异可以通过使用相同材料的晶体管对的栅极的离子注入的不同值，或通过使用不同材料的剂量来产生。 也可以通过使用不同的晶体管沟道长度来获得阈值电压的差异。 也可以通过使用电压控制衬底装置控制晶体管衬底电压来调制阈值电压。