公开(公告)号：US20170200786A1

公开(公告)日：2017-07-13

申请号：US14993543

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L29/06 ,  H01L27/11 ,  H01L21/308 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3065

CPC classification number: H01L29/0692 ,  H01L21/3086 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Shaped mandrels are used to form closed-loop spacer(s) around the shaped mandrels, after which the shaped mandrels are removed, leaving a closed-loop fin. A transistor includes U-shaped portion(s) of a closed-loop fin, and a gate across channel region(s) of the U-shaped portion(s) of a closed-loop fin. A semiconductor structure includes portion(s) of closed-loop fin(s), and transistors formed from the portion(s) of closed-loop fin(s).

公开(公告)号：US20160372559A1

公开(公告)日：2016-12-22

申请号：US14740872

申请日：2015-06-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG

IPC: H01L29/417 ,  H01L21/306 ,  H01L29/08 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Semiconductor devices and methods for forming the devices with fin contacts. One method includes, for instance: obtaining a wafer with at least one isolation region; forming at least one fin on the wafer; forming at least one sacrificial contact; forming at least one sacrificial gate; etching to recess the at least one fin; growing an epitaxial material over the at least one fin; performing replacement metal gate to the at least one sacrificial gate; depositing an interlayer dielectric layer; and forming at least one fin contact. An intermediate semiconductor device is also disclosed.

Abstract translation: 用于形成具有翅片触点的器件的半导体器件和方法。 一种方法包括例如：获得具有至少一个隔离区域的晶片; 在所述晶片上形成至少一个翅片; 形成至少一个牺牲接触; 形成至少一个牺牲栅极; 蚀刻以使所述至少一个翅片凹陷; 在所述至少一个翅片上生长外延材料; 对所述至少一个牺牲栅极执行替换金属栅极; 沉积层间电介质层; 并形成至少一个翅片接触件。 还公开了一种中间半导体器件。

公开(公告)号：US20160276345A1

公开(公告)日：2016-09-22

申请号：US15049391

申请日：2016-02-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Bingwu LIU ,  Hui ZANG ,  Lun ZHAO

IPC: H01L27/088 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/3083 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Method for forming FinFET source/drain regions with reduced field oxide loss and the resulting devices are disclosed. Embodiments include forming silicon fins separated by a field oxide on a silicon substrate; recessing the field oxide to reveal an upper portion of the silicon fins; forming a spacer layer conformally over the upper portion of the fins and over the field oxide; filling spaces between the fins with a material having high selectivity with the spacer layer; recessing the material; removing the spacer layer above an upper surface of the material; removing the material; recessing the upper portion of the fins; and epitaxially growing source/drain regions on the recessed fins.

Abstract translation: 公开了用于形成具有减小的场氧化物损耗的FinFET源极/漏极区域的方法以及所得到的器件。 实施例包括在硅衬底上形成由场氧化物分离的硅散热片; 凹陷场氧化物以露出硅散热片的上部; 在翅片的上部和场氧化物上方形成间隔层; 用具有间隔层的高选择性的材料填充翅片之间的空间; 凹陷材料; 在所述材料的上表面上方移除所述间隔层; 去除材料; 使翅片的上部凹陷; 并且在凹陷散热片上外延生长源极/漏极区域。

公开(公告)号：US20160225791A1

公开(公告)日：2016-08-04

申请号：US14609115

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a multilayer structure, the multilayer structure having a bulk substrate, a first layer defining an ultrathin body spaced apart from the bulk substrate, and a second layer above the first layer having material for defining a fin, and patterning the second layer to define a fin above the ultrathin body.

Abstract translation: 为了制造半导体结构，这里提出了一种制造半导体结构的方法，该方法包括形成多层结构，该多层结构具有体基片，限定与本体衬底间隔开的超薄体的第一层， 并且在第一层之上的第二层具有用于限定翅片的材料，并且图案化第二层以限定超薄体上方的翅片。

公开(公告)号：US20150287725A1

公开(公告)日：2015-10-08

申请号：US14245656

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG

IPC: H01L27/092 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, a second field effect transistor formed in the substrate structure, and a third field effect transistor formed in the substrate structure. The first field effect transistor can include a first gate stack configuration, and a first threshold voltage. The second field effect transistor can include a second gate stack configuration, and a second threshold voltage. The third field effect transistor can include a third gate stack configuration, and a third threshold voltage.

Abstract translation: 在一个方面，这里阐述了具有形成在衬底结构中的第一场效应晶体管，形成在衬底结构中的第二场效应晶体管和形成在衬底结构中的第三场效应晶体管的半导体器件。 第一场效应晶体管可以包括第一栅极堆叠配置和第一阈值电压。 第二场效应晶体管可以包括第二栅极堆叠配置和第二阈值电压。 第三场效应晶体管可以包括第三栅极堆叠配置和第三阈值电压。

公开(公告)号：US20150179766A1

公开(公告)日：2015-06-25

申请号：US14135716

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporations

Inventor： Hui ZANG ,  Chun-chen YEH ,  Tenko YAMASHITA ,  Veeraraghavan BASKER

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L29/41791 ,  H01L29/785

Abstract: A method for fabricating a finfet with a buried local interconnect and the resulting device are disclosed. Embodiments include forming a silicon fin on a BOX layer, forming a gate electrode perpendicular to the silicon fin over a portion of the silicon fin, forming a spacer on each of opposite sides of the gate electrode, forming source/drain regions on the silicon fin at opposite sides of the gate electrode, recessing the BOX layer, undercutting the silicon fin and source/drain regions, at opposite sides of the gate electrode, and forming a local interconnect on a recessed portion of the BOX layer.

Abstract translation: 公开了一种用于制造具有埋入局部互连的鳍片的方法，以及所得到的器件。 实施例包括在BOX层上形成硅翅片，在硅鳍片的一部分上形成垂直于硅鳍片的栅电极，在栅电极的每个相对侧上形成间隔物，在硅片上形成源极/漏极区域 在栅电极的相对侧，使BOX层凹陷，在栅电极的相对侧处切割硅鳍和源极/漏极区，并在BOX层的凹陷部分上形成局部互连。

公开(公告)号：US20150168824A1

公开(公告)日：2015-06-18

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei SUN ,  Chanro PARK ,  Wenhui WANG ,  Hui ZANG

IPC: G03F1/62 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。