公开(公告)号：US09379104B1

公开(公告)日：2016-06-28

申请号：US14639159

申请日：2015-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/423 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/0629 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/845 ,  H01L27/0255 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/861

Abstract: Methods for preparing a FinFET device with a protection diode formed prior to M1 formation and resulting devices are disclosed. Embodiments include forming plural fins on a substrate, with a STI region between adjacent fins; forming a dummy gate stack over and perpendicular to the fins, the gate stack including a dummy gate over a dummy gate insulating layer; forming sidewall spacers on opposite sides of the dummy gate stack; forming source/drain regions at opposite sides of the dummy gate stack; forming an ILD over the STI regions between fins; removing the dummy gate stack forming a gate cavity; forming a gate dielectric in the gate cavity; removing the gate dielectric from the gate cavity in a protection diode area, exposing an underlying fin; implanting a dopant into the exposed fin; and forming a RMG in the gate cavity, wherein a protection diode is formed in the protection diode area.

Abstract translation: 公开了在形成M1形成之前形成保护二极管的FinFET器件的制备方法。 实施例包括在基板上形成多个翅片，其中在相邻翅片之间具有STI区域; 在所述散热片上方形成虚拟栅极堆叠并且垂直于所述散热片，所述栅极堆叠包括虚拟栅极绝缘层上的伪栅极; 在所述伪栅极堆叠的相对侧上形成侧壁间隔物; 在虚拟栅极堆叠的相对侧形成源极/漏极区域; 在翅片之间的STI区域上形成ILD; 去除形成门腔的虚拟栅极堆叠; 在栅腔中形成栅极电介质; 在保护二极管区域中从栅极腔去除栅极电介质，暴露下面的鳍; 将掺杂剂注入暴露的翅片中; 以及在所述栅极腔中形成RMG，其中在所述保护二极管区域中形成保护二极管。

公开(公告)号：US09142640B1

公开(公告)日：2015-09-22

申请号：US14306864

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiaodong Yang ,  Yanxiang Liu ,  Jin Ping Liu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A non-planar transistor is fabricated with dummy or sacrificial epitaxy and a structure for subsequent replacement or final epitaxy containment is created around the sacrificial epitaxy. The dummy epitaxy is then removed and replaced with the replacement epitaxy. The containment structure allows for uniform growth of the replacement epitaxy and prevents merger. Where n-type and p-type structures are present, the replacement epitaxy process is performed for each type, while protecting the other type with a mask. Optionally, one of the replacement epitaxies, i.e., the one for n-type or p-type, may be used as the dummy epitaxy, resulting in the need for only one mask.

Abstract translation: 用虚拟或牺牲外延制造非平面晶体管，并且在牺牲外延周围产生用于后续替换或最终外延容纳的结构。 然后去除虚拟外延并用替换外延代替。 容纳结构允许替代外延的均匀生长并且防止合并。 在存在n型和p型结构的情况下，对于每种类型进行替换外延工艺，同时用掩模保护另一种类型。 任选地，替代的外延（即，用于n型或p型的）中的一种可以用作虚拟外延，导致仅需要一个掩模。

公开(公告)号：US10468310B2

公开(公告)日：2019-11-05

申请号：US15334964

申请日：2016-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

公开(公告)号：US20190221515A1

公开(公告)日：2019-07-18

申请号：US15872589

申请日：2018-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Jianwei Peng ,  Xusheng Wu ,  Yi Qi ,  Jeffrey Chee

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

公开(公告)号：US20190081175A1

公开(公告)日：2019-03-14

申请号：US15702278

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Hong Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves forming a sigma shaped source/drain lattice. A fin is formed on a semiconductor substrate. A gate region is formed over the fin. In a source region and a drain region adjacent bottom portions of the fin, a first recess cavity is formed in the source region, and a second recess cavity is formed in the drain region. The first and second recess cavities comprise sidewalls formed in an angle relative to a vertical axis. Portions of the first and second recess cavities extend below the fin. In the first recess cavity, a first rare earth oxide layer is formed, and in the second recess cavity, a second rare earth oxide layer is formed.

公开(公告)号：US10181468B2

公开(公告)日：2019-01-15

申请号：US15338512

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ziyan Xu ,  Chengwen Pei ,  Xusheng Wu

IPC: H01L29/51 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

公开(公告)号：US10068810B1

公开(公告)日：2018-09-04

申请号：US15697661

申请日：2017-09-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Sipeng Gu

IPC: H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/308

Abstract: A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins may be formed by etching an active epitaxial layer that is disposed over the substrate. An intervening sacrificial epitaxial layer may be used to template growth of the active epitaxial layer, and is then removed and backfilled with an isolation dielectric layer. The isolation dielectric layer may be disposed between bottom surfaces of the fins and the substrate, and may be deposited, for example, following the etching process used to define the fins. Within different regions of the substrate, dielectrically isolated fins of different heights may have substantially co-planar top surfaces.

公开(公告)号：US20180248046A1

公开(公告)日：2018-08-30

申请号：US15445392

申请日：2017-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Jiehui Shu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L21/02532 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78684

Abstract: A plurality of vertically oriented channel semiconductor structures is formed above a substrate. A bottom source/drain (S/D) region is formed proximate a lower portion of the vertically oriented channel semiconductor structure. A first dielectric layer is formed above the vertically oriented channel semiconductor structure. A thickness of the first dielectric layer is reduced to expose an upper portion of the vertically oriented channel semiconductor structure. A first semiconductor material region is formed on the exposed upper portion. The thickness of the first dielectric layer is further reduced to expose a channel portion of the vertically oriented channel semiconductor structure and to define a bottom spacer adjacent the bottom S/D region. A gate structure is formed around the channel region of the vertically oriented channel semiconductor structure. A second semiconductor material region is formed on the upper portion to define an upper S/D region after forming the gate structure.

公开(公告)号：US10014409B1

公开(公告)日：2018-07-03

申请号：US15393400

申请日：2016-12-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  David Paul Brunco

IPC: H01L29/732 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US09972621B1

公开(公告)日：2018-05-15

申请号：US15483344

申请日：2017-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Chengwen Pei ,  Ziyan Xu

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02236 ,  H01L21/31053 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.