公开(公告)号：US20240006289A1

公开(公告)日：2024-01-04

申请号：US17853204

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Kemal Aygun ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Zhiguo Qian ,  Jiwei Sun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L23/552 ,  H01L21/4853 ,  H01L21/76877 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/3025

Abstract: An electronic device includes a substrate including a core layer having a first surface and a second surface opposite the first surface, and at least one coaxial through-hole extending vertically through the core layer from the first surface to the second surface. The coaxial through-hole includes at least a first through-via that includes electrically conductive material extending through the core layer from the first surface to the second surface, and a conductive layer including the same or different electrically conductive material extending vertically through the core layer from the first surface to the second surface and surrounding the first through-via. The conductive layer is to be connected to a ground voltage and is electrically isolated from the first through-via.

公开(公告)号：US20230420347A1

公开(公告)日：2023-12-28

申请号：US17847282

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Cemil Geyik ,  Zhiguo Qian ,  Kristof Kuwawi Darmawikarta ,  Zhichao Zhang ,  Kemal Aygun

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4857 ,  H01L25/0652

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a first face and an opposing second face, the package substrate comprising a conductive trace in a dielectric material, a conductive structure at least partially surrounding the conductive trace and separated from the conductive trace by the dielectric material; and an integrated circuit (IC) die attached to the first face of the package substrate and coupled to the conductive trace by a conductive pathway through the package substrate. The conductive trace has a non-rectangular cross-section with rounded corners, the conductive structure comprises a plurality of conductive planes parallel to the conductive trace and coupled to a ground connection.

公开(公告)号：US11682613B2

公开(公告)日：2023-06-20

申请号：US17360701

申请日：2021-06-28

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Kaladhar Radhakrishnan ,  Kemal Aygun

IPC: H01L23/49 ,  H01L23/64 ,  H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/68 ,  H01L23/49827 ,  H01L24/17 ,  H01L23/5384 ,  H01L2224/08165 ,  H01L2224/16157 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24221 ,  H01L2224/32165 ,  H01L2224/32235 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2924/30111

Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20230103183A1

公开(公告)日：2023-03-30

申请号：US17485045

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas V. Pietambaram ,  Kemal Aygun ,  Telesphor Kamgaing ,  Zhiguo Qian ,  Jiwei Sun

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a TGV. The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

公开(公告)号：US11450629B2

公开(公告)日：2022-09-20

申请号：US16643554

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Kemal Aygun ,  Zhi Guo Qian ,  Jian Yong Xie

IPC: H01L23/66 ,  H01P3/16

Abstract: An interposer layer includes an integral waveguide to facilitate high speed (e.g., greater than 80 GHz) communication between semiconductor dies in a semiconductor package. An interposer layer may include a waveguide member and a dielectric layer disposed adjacent at least a portion of an exterior perimeter of the waveguide member. The waveguide member includes a material having a first relative permittivity. The dielectric member includes a material having a second relative permittivity that is less than the first relative permittivity. The waveguide member and the dielectric member form an interposer layer having an upper surface and a lower surface. A first conductive sheet may be disposed proximate the upper surface of the interposer layer and a second conductive sheet may be disposed proximate the lower surface of the interposer layer.

公开(公告)号：US11296031B2

公开(公告)日：2022-04-05

申请号：US16769548

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Kemal Aygun ,  Zhiguo Qian ,  Jianyong Xie

IPC: H01L23/538 ,  H01L21/762 ,  H01L29/06 ,  H01L21/765 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

公开(公告)号：US11222847B2

公开(公告)日：2022-01-11

申请号：US16469084

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US11212932B2

公开(公告)日：2021-12-28

申请号：US16888069

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Zhichao Zhang ,  Kemal Aygun

IPC: H01R12/00 ,  H05K7/10 ,  H05K1/11 ,  H05K7/14 ,  H05K1/02

Abstract: An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

公开(公告)号：US20210257309A1

公开(公告)日：2021-08-19

申请号：US16793951

申请日：2020-02-18

Applicant: INTEL CORPORATION

Inventor： Srinivas V. Pietambaram ,  Rahul N. Manepalli ,  Cemil S. Geyik ,  Kemal Aygun

IPC: H01L23/532 ,  H01L21/768

Abstract: Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material. The first and second layers may be discrete layers or a single continuous layer with grading.

公开(公告)号：US10992342B2

公开(公告)日：2021-04-27

申请号：US16483019

申请日：2017-03-01

Applicant: Intel Corporation

Inventor： Yidnekachew S. Mekonnen ,  Kemal Aygun ,  Henning Braunisch

IPC: H04B3/32 ,  H04B3/487 ,  H04L25/08

Abstract: Technology for simplified multimode signaling includes determining first and second self α-terms, cross coupling α-terms, and a delay skew term. For each communication link bundled in groups, the signals can be modulated as a superposition of the signals delayed and weighted based on the first and second self α-terms, the cross coupling α-terms and the delay skew term.