公开(公告)号：US20200381296A1

公开(公告)日：2020-12-03

申请号：US16428008

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Ruilong Xie ,  Andrew Greene ,  Veeraraghavan S. Basker

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02

Abstract: A method includes applying a first dielectric material onto a semiconductor substrate to form a first dielectric layer on the semiconductor substrate, creating a plurality of trenches in the dielectric layer, depositing a sacrificial material within the trenches of the dielectric layer, removing the sacrificial material from at least a first segment of a first trench of the trenches, depositing a second dielectric fill material into the first segment of the first trench where the sacrificial material was removed, removing the sacrificial material from at least some of the remaining trenches and depositing a metallic material within the first trench to define at least first and second lines in the first trench and form a metallic interconnect structure.

公开(公告)号：US10818548B1

公开(公告)日：2020-10-27

申请号：US16426199

申请日：2019-05-30

Applicant: International Business Machines Corporation

Inventor： Kafai Lai ,  Chih-Chao Yang ,  Yongan Xu ,  Su Chen Fan

IPC: H01L21/768 ,  H01L29/417 ,  H01L21/3213 ,  H01L27/088

Abstract: Various semiconductor fabrication methods and structures are disclosed for cost effectively fabricating a self-aligned contact. A source-drain active region is on a substrate and horizontally extends to sidewall spacers of two adjacent gate stacks on the substrate. A conductive material layer including Titanium is formed by selective deposition on the source-drain active area. An interlevel dielectric (ILD) layer is deposited over the source-drain active area and the two gate stacks. Vertical directional etching in the ILD layer forms a vertical trench contacting the conductive material layer. Selective wet etching in the vertical trench selectively etches the conductive material layer and forms a void therein. Deposition of a second conductive material in the vertical trench fills the vertical trench, including the void, and the second conductive material contacts the top surface of the source-drain active area to form a source-drain self-aligned contact.

公开(公告)号：US10658190B2

公开(公告)日：2020-05-19

申请号：US16139819

申请日：2018-09-24

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.

公开(公告)号：US20200090990A1

公开(公告)日：2020-03-19

申请号：US16685142

申请日：2019-11-15

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Hemanth Jagannathan ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.

公开(公告)号：US20200090989A1

公开(公告)日：2020-03-19

申请号：US16133785

申请日：2018-09-18

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Hemanth Jagannathan ,  Raghuveer R. Patlolla ,  Cornelius Brown Peethala

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.

公开(公告)号：US10332971B2

公开(公告)日：2019-06-25

申请号：US15826346

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Johnathan E. Faltermeier ,  Su Chen Fan ,  Sivananda K. Kanakasabapathy ,  Injo Ok ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/84

Abstract: A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer.

公开(公告)号：US10217664B2

公开(公告)日：2019-02-26

申请号：US15909462

申请日：2018-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lawrence A. Clevenger ,  Su Chen Fan ,  Huai Huang ,  Koichi Motoyama ,  Wei Wang ,  Chih-Chao Yang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

Abstract: A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

公开(公告)号：US10186599B1

公开(公告)日：2019-01-22

申请号：US15655547

申请日：2017-07-20

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Chen Fan ,  Andrew M. Greene ,  Sean Lian ,  Balasubramanian Pranatharthiharan ,  Mark V. Raymond ,  Ruilong Xie

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/033 ,  H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L29/51

Abstract: Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided. In one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers in a dielectric; forming gate trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.

公开(公告)号：US20180337257A1

公开(公告)日：2018-11-22

申请号：US15813528

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Zuoguang Liu ,  Heng Wu ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/768 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/7827

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having an embedded bottom metal contact. A semiconductor fin is formed on a doped region of a substrate. A portion of the doped region adjacent to the semiconductor fin is recessed and an embedded contact is formed on the recessed portion. A material of the conductive rail is selected such that a conductivity of the embedded contact is higher than a conductivity of the doped region.

公开(公告)号：US10128352B2

公开(公告)日：2018-11-13

申请号：US15432372

申请日：2017-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.