公开(公告)号：US06436840B1

公开(公告)日：2002-08-20

申请号：US09691188

申请日：2000-10-19

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Qi Xiang

IPC分类号： H01L21302

CPC分类号： H01L21/28194 ,  H01L21/28044 ,  H01L21/3146 ,  H01L29/4941 ,  H01L29/517 ,  Y10S438/926

摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. A barrier is then deposited on the CVD amorphous silicon layer. A metal is then formed on the barrier. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer. The work function is preserved by the barrier during subsequent high temperature processing, due to the barrier which prevents interaction between the CVD amorphous silicon layer and the metal, which could otherwise form silicide and change the work function.

摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。 然后在CVD非晶硅层上沉积阻挡层。 然后在屏障上形成金属。 由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。 由于防止CVD非晶硅层与金属之间的相互作用的屏障，因此在随后的高温处理期间，阻挡层保留功函数，否则可能形成硅化物并改变功函数。

公开(公告)号：US06420770B1

公开(公告)日：2002-07-16

申请号：US09882244

申请日：2001-06-15

申请人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

发明人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC分类号： H01L2900

CPC分类号： H01L29/665 ,  H01L21/76224

摘要： STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

摘要翻译： 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。

公开(公告)号：US06239452B1

公开(公告)日：2001-05-29

申请号：US09320682

申请日：1999-05-27

申请人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

发明人： Qi Xiang ,  Shekhar Pramanick ,  Ming-Ren Lin

IPC分类号： H01L2184

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/665

摘要： A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.

摘要翻译： 提供了具有自对准硅化物栅极结构的深亚微米MOS器件及其形成方法，以克服多Si耗尽和硼渗透的问题。 在栅极氧化物和多晶硅栅电极之间形成第一镍硅化物层。 此外，第二镍硅化物层形成在高掺杂源/漏区上。 以这种方式，MOS器件的可靠性将得到提高。

公开(公告)号：US06218245B1

公开(公告)日：2001-04-17

申请号：US09198654

申请日：1998-11-24

申请人： Qi Xiang ,  Xiao-Yu Li

发明人： Qi Xiang ,  Xiao-Yu Li

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11558 ,  Y10S438/91

摘要： A method for fabricating a high-density and high-reliability EEPROM device includes providing a semiconductor substrate having both an EEPROM cell region, and a peripheral MOS transistor region. A gate oxide layer is formed to overlie the peripheral MOS transistor region and the EEPROM cell region. A tunnel oxide region is formed to overlie a portion of the EEPROM cell region. Then, a polycrystalline silicon layer is formed to overlie both the gate oxide layer and the tunnel oxide region. A deuterium annealing process is then carried out to anneal the gate oxide layer and the tunnel oxide region. The polycrystalline silicon layer is patterned to form numerous gate electrodes including gate electrodes for peripheral transistors, floating-gate transistors, and read and write transistors in the EEPROM cell.

摘要翻译： 一种用于制造高密度和高可靠性EEPROM器件的方法包括提供具有EEPROM单元区域和外围MOS晶体管区域的半导体衬底。 形成栅极氧化层以覆盖外围MOS晶体管区域和EEPROM单元区域。 形成隧道氧化物区域以覆盖EEPROM单元区域的一部分。 然后，形成多晶硅层以覆盖栅极氧化物层和隧道氧化物区域两者。 然后进行氘退火处理以退火栅极氧化物层和隧道氧化物区域。 图案化多晶硅层以形成多个栅电极，其包括用于外围晶体管的栅电极，浮栅晶体管以及EEPROM单元中的读写晶体管。

公开(公告)号：US6087696A

公开(公告)日：2000-07-11

申请号：US86437

申请日：1998-05-28

申请人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

发明人： Xiao-Yu Li ,  Qi Xiang ,  Sunil D. Mehta

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L21/28194 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/513 ,  H01L29/517 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518

摘要： An improved EEPROM cell structure and a method of fabricating the same is provided so as to improve data retention. The EEPROM cell includes a stacked dielectric structure consisting of a thin tunnel oxide layer and a high-k dielectric layer to function as the tunneling dielectric barrier so as to suppress leakage current.

摘要翻译： 提供了改进的EEPROM单元结构及其制造方法，以便改善数据保留。 EEPROM单元包括由薄的隧道氧化物层和高k电介质层构成的叠层电介质结构，用作隧道电介质势垒，以便抑制漏电流。

公开(公告)号：US6060377A

公开(公告)日：2000-05-09

申请号：US306874

申请日：1999-05-07

申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

IPC分类号： H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0338 ,  H01L21/28123 ,  H01L29/6659

摘要： A polysilicon structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a masking polysilicon structure having a first predetermined length defined by sidewalls on ends of the first predetermined length of the masking polysilicon structure. The present invention also includes a step of depositing a layer of metal on the sidewalls of the masking polysilicon structure. The layer of metal has a predetermined thickness. The layer of metal reacts with the masking polysilicon structure at the sidewalls of the masking polysilicon structure in a silicidation anneal to form metal silicide. The masking polysilicon structure has a second predetermined length that is reduced from the first predetermined length when the metal silicide has consumed into the sidewalls of the masking polysilicon structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of metal deposited on the sidewalls of the masking polysilicon structure. The masking polysilicon structure has the second predetermined length and is used as a mask for etching a first layer of polysilicon to form the polysilicon structure from the first layer of polysilicon. The remaining polysilicon structure after this etch has the reduced length that is substantially equal to the second predetermined length of the masking polysilicon structure. The present invention may be used to particular advantage when the polysilicon structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的多晶硅结构，其超过通过光刻实现的结果。 通常，本发明包括形成具有由掩模多晶硅结构的第一预定长度的端部上的侧壁限定的第一预定长度的掩模多晶硅结构的步骤。 本发明还包括在掩模多晶硅结构的侧壁上沉积金属层的步骤。 金属层具有预定的厚度。 金属层在硅化退火中在掩模多晶硅结构的侧壁处与掩模多晶硅结构反应以形成金属硅化物。 掩模多晶硅结构具有第二预定长度，当在硅化退火之后金属硅化物消耗到掩模多晶硅结构的侧壁时，该第二预定长度从第一预定长度减小。 第二预定长度取决于沉积在掩模多晶硅结构的侧壁上的金属层的预定厚度。 掩模多晶硅结构具有第二预定长度，并且用作蚀刻第一多晶硅层的掩模，以从第一多晶硅层形成多晶硅结构。 在该蚀刻之后的剩余多晶硅结构具有基本上等于掩模多晶硅结构的第二预定长度的减小的长度。 当具有减小的长度的多晶硅结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以特别有利。

公开(公告)号：US08735050B2

公开(公告)日：2014-05-27

申请号：US13567233

申请日：2012-08-06

申请人： Lei Yuan ,  Hidekazu Yoshida ,  Jongwook Kye ,  Qi Xiang ,  Mahbub Rashed

发明人： Lei Yuan ,  Hidekazu Yoshida ,  Jongwook Kye ,  Qi Xiang ,  Mahbub Rashed

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G03F7/70466 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 一种方法包括创建包括第一和第二相邻单元格的主图案布局。 第一相邻单元具有带有第一路由线的第一边界引脚。 第二相邻单元具有带有第二路由线的第二边界引脚。 第一和第二路由线重叠以限定边缘线迹以耦合第一和第二边界引脚。 主模式布局被分解为子模式。

公开(公告)号：US07462549B2

公开(公告)日：2008-12-09

申请号：US10755602

申请日：2004-01-12

申请人： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

发明人： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

IPC分类号： H01L21/76

CPC分类号： H01L29/66742 ,  H01L21/76283 ,  H01L29/458 ,  H01L29/7842 ,  H01L29/78687 ,  Y10S438/933

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 在形成沟槽之后形成应变材料。 该方法可以用在盒层上方的化合物半导体层上。

公开(公告)号：US20080237803A1

公开(公告)日：2008-10-02

申请号：US11691332

申请日：2007-03-26

申请人： Witold P. Maszara ,  Qi Xiang

发明人： Witold P. Maszara ,  Qi Xiang

IPC分类号： H01L29/06

CPC分类号： H01L21/0337

摘要： A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.

摘要翻译： 提供一种用于形成半导体器件的方法，包括处理具有间隔层和结构层的晶片，间隔层在结构层之上。 该方法继续，包括从间隔层形成第一侧壁间隔物，从第一侧壁间隔物下方的结构层形成结构带，在结构带上方形成掩模结构，并与结构带相交并形成从结构带下方的垂直柱 掩蔽结构。

公开(公告)号：US07217608B1

公开(公告)日：2007-05-15

申请号：US10620605

申请日：2003-07-17

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L27/092

摘要： Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

摘要翻译： 由于PMOS晶体管中的空穴的迁移率小于NMOS晶体管中的电子的迁移率，所以传统的CMOS器件遭受不平衡。 由于应变硅提供比空穴迁移率更大的电子迁移率增加，在CMOS器件的通道中使用应变硅进一步加剧了电子和空穴迁移率的差异。 然而，在应变硅层下面的SiGe层中的空穴迁移率增加。 因此，通过在NMOS晶体管中包括应变硅而不是在CMOS器件的PMOS晶体管中形成更平衡的高速CMOS器件。