利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

112 条记录 (耗时 0.049 秒)

    Ferroelectric Memory Cell Arrays and Method of Operating the Same
    81.
    发明申请
    Ferroelectric Memory Cell Arrays and Method of Operating the Same 审中-公开
    铁电存储器单元阵列及其操作方法

    公开(公告)号：US20100110753A1

    公开(公告)日：2010-05-06

    申请号：US12262830

    申请日：2008-10-31

    申请人： Stefan Slesazeck ,  Rolf Weis ,  Stefan Jakschik

    发明人： Stefan Slesazeck ,  Rolf Weis ,  Stefan Jakschik

    IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C11/34 ,  H01L21/20

    CPC分类号： H01L27/1159 ,  G11C5/063 ,  G11C11/22 ,  G11C11/223 ,  H01L27/0207 ,  H01L27/11592 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

    摘要： An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.

    摘要翻译： 集成电路包括多个开关器件，其中每个器件包括能够承受至少第一和第二极化状态的栅极电介质。 集成电路还包括地址电路，其被配置为控制电耦合到开关器件的负载路径的第一负载区域的位线和与开关器件的栅极电耦合的字线。 地址电路被配置为控制写入周期，使得在所选择的开关器件的栅极电介质处感应出第一电压，并且在非选择的开关器件的栅极电介质处感应出第二电压。 第一电压足以将所选择的器件的栅极电介质从第一极化状态切换到第二极化状态，并且第二电压不足以切换未选择器件的栅极电介质。

    Memory Scheduler for Managing Internal Memory Operations
    82.
    发明申请
    Memory Scheduler for Managing Internal Memory Operations 有权
    用于管理内部存储器操作的内存调度器

    公开(公告)号：US20100058018A1

    公开(公告)日：2010-03-04

    申请号：US12202581

    申请日：2008-09-02

    申请人： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

    发明人： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

    IPC分类号： G06F12/00

    CPC分类号： G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431

    摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

    摘要翻译： 集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。 存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。 存储器调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

    INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE
    84.
    发明申请
    INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE 有权
    集成电路，包括U形形式的访问设备

    公开(公告)号：US20090206315A1

    公开(公告)日：2009-08-20

    申请号：US12033519

    申请日：2008-02-19

    申请人： Rolf Weis ,  Thomas Happ

    发明人： Rolf Weis ,  Thomas Happ

    IPC分类号： H01L45/00

    CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

    摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.

    摘要翻译： 集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。 集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

    STORAGE CAPACITOR AND METHOD OF MANUFACTURING A STORAGE CAPACITOR
    86.
    发明申请
    STORAGE CAPACITOR AND METHOD OF MANUFACTURING A STORAGE CAPACITOR 有权
    存储电容器和存储电容器的制造方法

    公开(公告)号：US20080001201A1

    公开(公告)日：2008-01-03

    申请号：US11856409

    申请日：2007-09-17

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/91

    摘要： An integrated circuit including a storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

    摘要翻译： 公开了一种包括适用于DRAM单元的存储电容器的集成电路，以及制造这种存储电容器的方法。 存储电容器至少部分地形成在半导体衬底表面上方。 本发明还包括采用存储电容器的存储器阵列。

    Fabricating a memory cell arrangement
    87.
    发明申请
    Fabricating a memory cell arrangement 审中-公开
    制作记忆单元布置

    公开(公告)号：US20060057814A1

    公开(公告)日：2006-03-16

    申请号：US11220918

    申请日：2005-09-08

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L29/945

    摘要： A method is described for fabricating a DRAM memory cell, which includes a trench capacitor and a select transistor. After the capacitor trench has been etched and optionally the first capacitor electrode has been produced, the trench is filled with a dummy filling. After the gate electrode and the first and second source/drain regions have been provided, the dummy filling is removed, and the capacitor dielectric and the second capacitor electrode are provided. As a result, it is possible to use temperature-sensitive materials for the capacitor dielectric and the second capacitor electrode despite the use of high-temperature steps. In the memory cell arrangement formed by this method, the direction of the conductive channel, which connects first and second source/drain regions to one another, can differ from the direction of the bit lines and of the word lines (e.g., by 45°).

    摘要翻译： 描述了一种用于制造包括沟槽电容器和选择晶体管的DRAM存储单元的方法。 在蚀刻电容器沟槽并且任选地已经生产第一电容器电极之后，沟槽填充有虚拟填充物。 在设置了栅极电极和第一和第二源极/漏极区域之后，去除虚拟填充物，并且提供电容器电介质和第二电容器电极。 结果，尽管使用高温步骤，也可以使用用于电容器电介质和第二电容器电极的温度敏感材料。 在通过该方法形成的存储单元布置中，将第一和第二源极/漏极区域彼此连接的导电沟道的方向可以不同于位线和字线的方向（例如，45° ）。

    Vertical transistor and transistor fabrication method
    88.
    发明授权
    Vertical transistor and transistor fabrication method 失效
    垂直晶体管和晶体管制造方法

    公开(公告)号：US06762443B2

    公开(公告)日：2004-07-13

    申请号：US10298834

    申请日：2002-11-18

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L27148

    CPC分类号： H01L29/78612 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/78642

    摘要： In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.

    摘要翻译： 在DRAM存储单元中，各个存储单元通过隔离沟槽（STI）彼此隔离。 在这种情况下，作为SOI晶体管由隔离沟槽形成垂直晶体管，因为其沟道区域通过隔离沟槽与衬底隔离。 例如在DRAM存储单元中使用的垂直晶体管和制造晶体管的方法包括通过在隔离沟槽中设置导电层来将垂直晶体管的沟道区域连接到衬底，该导电层位于下部绝缘填充物和 上部绝缘填充。

    Memory cell with trench capacitor and method of fabricating the memory cell
    89.
    发明授权
    Memory cell with trench capacitor and method of fabricating the memory cell 失效
    具有沟槽电容器的存储单元和制造存储单元的方法

    公开(公告)号：US06420239B2

    公开(公告)日：2002-07-16

    申请号：US09871010

    申请日：2001-05-31

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L218242

    CPC分类号： H01L27/10864 ,  H01L27/10876

    摘要： The memory cell has a trench in which a capacitor is formed. Furthermore, a vertical transistor is formed in the trench, above the trench capacitor. The doping regions of the vertical transistor are arranged in the substrate. In order to connect the gate electrode of the vertical transistor to a word line, a dielectric layer having an inner opening is arranged in the trench, above the gate electrode. The dielectric layer is configured as lateral edge webs which project beyond the cross section of the trench and thus cover part of the substrate. The lateral edge webs enable self-aligned formation of an isolation trench.

    摘要翻译： 存储单元具有形成电容器的沟槽。 此外，在沟槽电容器上方的沟槽中形成垂直晶体管。 垂直晶体管的掺杂区域布置在衬底中。 为了将垂直晶体管的栅电极连接到字线，在沟槽中布置具有内部开口的电介质层，栅电极上方。 电介质层被构造为横向边缘腹板，其突出超过沟槽的横截面并因此覆盖衬底的一部分。 横向边缘腹板使得能够自对准地形成隔离沟槽。

    Integrated circuit with at least two switches
    90.
    发明授权
    Integrated circuit with at least two switches 有权

    公开(公告)号：US09859274B2

    公开(公告)日：2018-01-02

    申请号：US13546555

    申请日：2012-07-11

    申请人： Rolf Weis

    发明人： Rolf Weis

    IPC分类号： H01L27/088 ,  H03K17/10

    CPC分类号： H01L27/0886 ,  H03K17/102

    摘要： A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.