公开(公告)号：US07741630B2

公开(公告)日：2010-06-22

申请号：US12028513

申请日：2008-02-08

申请人： Klaus-Dieter Ufert ,  Josef Willer

发明人： Klaus-Dieter Ufert ,  Josef Willer

IPC分类号： H01L47/00

CPC分类号： H01L27/101 ,  H01L27/222 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1625 ,  H01L45/1675

摘要： An integrated circuit including a memory cell and a method of manufacturing the integrated circuit are described. The memory cell includes a buried gate select transistor and a resistive memory element coupled to the buried gate select transistor. The resistive memory element stores information based on a resistivity of the resistive memory element.

摘要翻译： 描述了包括存储单元的集成电路和集成电路的制造方法。 存储单元包括掩埋栅极选择晶体管和耦合到掩埋栅选择晶体管的电阻存储元件。 电阻性存储元件基于电阻式存储元件的电阻率存储信息。

公开(公告)号：US20080099834A1

公开(公告)日：2008-05-01

申请号：US11589303

申请日：2006-10-30

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inverter which is at least partially formed in a semiconductor substrate includes a first transistor with a first channel and a second transistor with a second channel, wherein each of the first and second transistors is formed as a FinFET with ridge shaped channels. The first and second gate electrodes of the first and second transistors are adjacent to the first and second channels on at least three sides of the corresponding channel. The first gate electrode extends from a top surface of the first channel ridge to a first ridge depth along the first channel, and the second gate electrode extends from a top surface of the second channel ridge to a second ridge depth along the second channel, wherein the first ridge depth is greater than the second ridge depth.

摘要翻译： 至少部分地形成在半导体衬底中的反相器包括具有第一通道的第一晶体管和具有第二通道的第二晶体管，其中第一和第二晶体管中的每一个形成为具有脊形沟道的FinFET。 第一和第二晶体管的第一和第二栅电极在相应通道的至少三侧上与第一和第二通道相邻。 第一栅电极从第一通道脊的顶表面沿第一通道延伸到第一脊深度，并且第二栅极从第二通道脊的顶表面延伸到沿第二通道的第二脊深度，其中 第一脊深度大于第二脊深度。

公开(公告)号：US20080029803A1

公开(公告)日：2008-02-07

申请号：US11497528

申请日：2006-08-02

申请人： Klaus Dieter Ufert ,  Josef Willer ,  David Abookasis

发明人： Klaus Dieter Ufert ,  Josef Willer ,  David Abookasis

IPC分类号： H01L29/788

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1226

摘要： The present invention relates to a reprogrammable non-volatile memory cell which comprises a selection transistor and a data storage element. The invention further relates to a method of fabricating such a memory cell, as well as to a memory cell array comprising a number of such memory cells.

摘要翻译： 本发明涉及一种可编程非易失性存储单元，其包括选择晶体管和数据存储元件。 本发明还涉及一种制造这种存储单元的方法，以及包括许多这种存储单元的存储单元阵列。

公开(公告)号：US20070257293A1

公开(公告)日：2007-11-08

申请号：US11429929

申请日：2006-05-08

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L29/42352 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117

摘要： The semiconductor memory device has a substrate with a main surface, on which parallel trenches are arranged. A memory layer is disposed at the sidewalls of the trenches, and gate electrodes are disposed in the trenches. Buried bitlines are formed as doped regions between neighboring trenches. The buried bitlines abut the sidewalls of the trenches and comprise upper surfaces, which are arranged at a specified distance from the bottom of the trenches. Source/drain regions are formed by sections of the buried bitlines.

摘要翻译： 半导体存储器件具有主表面的衬底，平行的沟槽布置在其上。 存储层设置在沟槽的侧壁处，栅电极设置在沟槽中。 埋置的位线形成为相邻沟槽之间的掺杂区域。 埋置的位线邻接沟槽的侧壁并且包括上表面，其布置在距离沟槽的底部指定的距离处。 源极/漏极区域由掩埋位线的部分形成。

公开(公告)号：US07280392B2

公开(公告)日：2007-10-09

申请号：US11339846

申请日：2006-01-26

申请人： Corvin Liaw ,  Josef Willer

发明人： Corvin Liaw ,  Josef Willer

IPC分类号： G11C11/00

CPC分类号： G11C13/0011 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/77 ,  H01L27/101

摘要： A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory cell is coupled between one of the first lines and one of the second lines. A checking unit determines whether to invert data values to be stored in memory cells coupled to at least a section of respective ones of the first lines based on a number of memory cells that would be programmed in the high-resistance state or the low-resistance state as a result of the data values in order to reduce the number memory cells programmed in the low-resistance state and the resulting leakage current.

摘要翻译： 存储器件包括存储器单元阵列，其包括具有非反应电阻的存储元件，其大小可编程为呈现高电阻状态或低电阻状态。 第一和第二行的集合提供对存储器单元的访问，其中每个存储器单元的存储元件耦合在第一行之一和第二行中的一个之间。 检查单元基于将以高电阻状态编程的存储器单元的数量或低电阻来确定是否反转要存储在耦合到第一行中的相应的第一行的至少一部分的存储器单元中的数据值 作为数据值的结果，为了减少在低电阻状态下编程的存储单元数量和所产生的漏电流。

公开(公告)号：US07250651B2

公开(公告)日：2007-07-31

申请号：US10921766

申请日：2004-08-19

申请人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

发明人： Karl-Heinz Küsters ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/792

摘要： Transistor bodies of semiconductor material located at a main surface of a semiconductor substrate between shallow trench isolations are provided with a rounded or curved upper surface. A floating gate electrode is arranged above said upper surface and electrically insulated from the semiconductor material by a tunnel dielectric having essentially the same tiny thickness throughout a primary tunnel area encompassing the area of curvature. The floating gate electrode may bridge the transistor body and is covered with a coupling dielectric provided for a control gate electrode, which forms part of a wordline.

摘要翻译： 位于浅沟槽隔离物之间的半导体衬底的主表面处的半导体材料的晶体管本体具有圆形或弯曲的上表面。 浮栅电极布置在所述上​​表面之上并且通过隧道电介质与半导体材料电绝缘，所述隧道电介质具有贯穿所述曲率区域的主隧道区域具有基本上相同的微小厚度。 浮栅电极可以桥接晶体管本体，并被形成为形成字线一部分的控制栅电极的耦合电介质覆盖。

公开(公告)号：US20070048993A1

公开(公告)日：2007-03-01

申请号：US11217122

申请日：2005-08-31

申请人： Josef Willer ,  Patrick Haibach ,  Christoph Kleint ,  Nicolas Nagel

发明人： Josef Willer ,  Patrick Haibach ,  Christoph Kleint ,  Nicolas Nagel

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11568

摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

摘要翻译： 半导体产品包括具有基板表面的基板。 多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。 在字线之间提供多个导电接触结构。 该产品还包括多个填充结构。 每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。 两个相应的接触结构在第一方向上彼此间隔一定距离。 在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。 衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

公开(公告)号：US07119395B2

公开(公告)日：2006-10-10

申请号：US10916013

申请日：2004-08-11

申请人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

发明人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

摘要翻译： 存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。 存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。 栅电极（5）通过导电间隔物（7）在侧面加宽。

公开(公告)号：US07087950B2

公开(公告)日：2006-08-08

申请号：US10835390

申请日：2004-04-30

申请人： Josef Willer ,  Frank Lau

发明人： Josef Willer ,  Frank Lau

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78645

摘要： The present invention relates to a flash memory cell comprising a silicon substrate having an active region comprising a channel region and source-/drain-regions, the active region comprising a projecting portion, which projecting portion at least comprising said channel region; a tunneling dielectric layer formed on the surface of said active region; a floating gate formed on the surface of said tunneling dielectric layer for storing electric charges; an inter-gates coupling dielectric layer formed on the surface of said floating gate, and a control gate formed on the surface of said inter-gates coupling dielectric layer, wherein said floating gate is formed to have a groove-like shape for at least partly encompassing said projecting portion of said active region. This invention further relates to a flash memory device comprising such flash memory cells, as well as a manufacturing method thereof.

摘要翻译： 本发明涉及一种闪存单元，其包括具有包括沟道区和源 - 漏区的有源区的硅衬底，所述有源区包括突出部分，所述突出部分至少包括所述沟道区; 形成在所述有源区的表面上的隧道电介质层; 形成在用于存储电荷的所述隧道介电层的表面上的浮动栅极; 形成在所述浮置栅极的表面上的栅极间耦合电介质层和形成在所述栅极间耦合电介质层的表面上的控制栅极，其中所述浮动栅极形成为具有至少部分地具有沟槽形状 包围所述有源区域的所述突出部分。 本发明还涉及一种包括这种闪存单元的闪速存储器件及其制造方法。

公开(公告)号：US20060145227A1

公开(公告)日：2006-07-06

申请号：US11371743

申请日：2006-03-09

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

摘要翻译： 本发明提供了一种用于存储单元阵列，特别是电荷捕获存储单元阵列的集成方案，其包括局部互连的架构，其能够避免字线堆叠的氮化物绝缘并且在标准技术中产生不同结构和尺寸的CMOS器件 以及更高级的存储单元晶体管。