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公开(公告)号：US20060134526A1
公开(公告)日：2006-06-22
申请号：US11283604
申请日：2005-11-17
CPC classification number: H01M2/166 , H01M2/145 , H01M2/18 , H01M10/0525
Abstract: A lithium ion secondary battery is provided. The lithium ion secondary battery generally comprises an electrode assembly, a container for accommodating the electrode assembly; and an electrolyte. The electrode assembly comprises two electrodes having opposite polarities and a separator. The separator comprises a porous membrane comprising clusters of ceramic particles. The porous membrane is formed by bonding the particle clusters with a binder. Each particle cluster is formed either by sintering or by dissolving and re-crystallizing all or a portion of the ceramic particles. The ceramic particles comprise a ceramic material having a band gap. Each particle cluster may have the shape of a grape bunch or a lamina, and may be formed by laminating scale or flake shaped ceramic particles.
Abstract translation: 提供锂离子二次电池。 锂离子二次电池通常包括电极组件，用于容纳电极组件的容器; 和电解质。 电极组件包括具有相反极性的两个电极和分离器。 分离器包括包含陶瓷颗粒簇的多孔膜。 多孔膜通过将颗粒团与粘合剂结合而形成。 每个颗粒簇通过烧结或通过溶解和重结晶全部或一部分陶瓷颗粒而形成。 陶瓷颗粒包括具有带隙的陶瓷材料。 每个颗粒簇可以具有葡萄束或层的形状，并且可以通过层压鳞片或片状陶瓷颗粒形成。
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公开(公告)号：US20050237094A1
公开(公告)日：2005-10-27
申请号：US11148783
申请日：2005-06-08
Applicant: Donald Stark , Jun Kim , Kurt Knorpp , Michael Ching , Natsuki Kushiyama
Inventor： Donald Stark , Jun Kim , Kurt Knorpp , Michael Ching , Natsuki Kushiyama
IPC: G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003
CPC classification number: H03K17/164 , G11C7/1051 , H03K19/00384
Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current 5 river receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
Abstract translation: 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出q-节点信号。 输出电流5河接收q节点信号，并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。
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83.发明申请公开(公告)号：US20050209738A1
公开(公告)日：2005-09-22
申请号：US10896845
申请日：2004-07-23
CPC classification number: G05B19/042 , G05B2219/25204 , G05B2219/2642
Abstract: A central control system for airconditioner(s) and a method for controlling the same. The central control system can centrally control a plurality of airconditioners connected to the same communication network. In the system, a protocol converter connected to a central controller converts a communication standard of a signal communicated between the airconditioners and the central controller into another communication standard, acquires connection state information by scanning connection state information of individual airconditioners, and transmits the acquired information to the central controller, such that a manager can correctly monitor an airconditioner state using the central controller, resulting in the implementation of a reliable control system.
Abstract translation: 空调中央控制系统及其控制方法。 中央控制系统可以集中控制连接到同一通信网络的多个空调器。 在该系统中，连接到中央控制器的协议转换器将在空调器和中央控制器之间传递的信号的通信标准转换为另一通信标准，通过扫描各个空调机的连接状态信息来获取连接状态信息，并且发送所获取的信息 到中央控制器，使得管理者可以使用中央控制器正确地监视空调器状态，从而实现可靠的控制系统。
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公开(公告)号：US20050096787A1
公开(公告)日：2005-05-05
申请号：US10976106
申请日：2004-10-28
Applicant: Jun Kim
Inventor： Jun Kim
Abstract: A tablet cassette control method of a medication dispensing and packaging system having a microcomputer, a medication dispensing unit with a plurality of tablet cassettes each mounted on a cassette rack, and a medication packaging unit disposed below the dispensing unit to package tablets released from the dispensing unit into a series of tablet containing paper bags, the control method comprises confirming the mounting of the tablet cassette on the cassette rack, applying a power to a memory in the tablet cassette to activate the memory, retrieving tablet information saved in the memory to the microcomputer, and breaking the power from the memory while maintaining operation of the system.
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85.发明申请Portable sliding-type digital communication device and locking apparatus thereof 审中-公开便携式滑动型数字通信装置及其锁定装置公开(公告)号：US20050054397A1
公开(公告)日：2005-03-10
申请号：US10917970
申请日：2004-08-13
Applicant: Jun Kim , In-Gon Park , Chang-Soo Lee , Jae-Shik Kim , Hong-Bae Kim
Inventor： Jun Kim , In-Gon Park , Chang-Soo Lee , Jae-Shik Kim , Hong-Bae Kim
CPC classification number: H04M1/0237 , G03B11/043 , H04M2250/52
Abstract: Disclosed herein is a portable sliding-up digital communication device. The portable sliding-type digital communication device comprises a body housing having a display unit located on the top surface thereof, the display unit comprising a first display area and a second display area disposed adjacent to the first display area, a sliding cover moved along the body housing in a sliding fashion such that the sliding cover is apart from the body housing or close to the body housing for exposing or covering the second display area, and holding means formed at the rear surfaces of the body housing and the sliding cover for maintaining a final sliding coupling position of the sliding cover to the body housing. The first display area is constantly viewable and the second display area is selectively coverable depending upon the position of the sliding cover.
Abstract translation: 这里公开了一种便携式上拉式数字通信装置。 便携式滑动式数字通信装置包括：主体壳体，其具有位于其顶表面上的显示单元，所述显示单元包括第一显示区域和邻近所述第一显示区域设置的第二显示区域，沿着所述第一显示区域移动的滑动盖 主体壳体以滑动方式使得滑动盖与主体壳体分离或靠近主体外壳以暴露或覆盖第二显示区域，以及形成在主体壳体和滑动盖的后表面处的保持装置，用于保持 滑动盖到主体壳体的最终滑动联接位置。 第一显示区域是可视的，第二显示区域可根据滑盖的位置选择性地覆盖。
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Patent Agency Ranking
86.发明授权SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same 有权具有用于防止浮体效应的身体接触的SOI MOSFET及其制造方法公开(公告)号：US06794716B2
公开(公告)日：2004-09-21
申请号：US09924787
申请日：2001-08-08
Applicant: Sung-bae Park , Jun Kim , Eun-han Kim , Hee-sung Kang , Young-wug Kim
Inventor： Sung-bae Park , Jun Kim , Eun-han Kim , Hee-sung Kang , Young-wug Kim
IPC: H01L2701
CPC classification number: H01L29/78615 , H01L29/78612
Abstract: An SOI MOSFET having a body contact for preventing the floating body effect is provided. The body contact is a trench perforating a body and a buried oxide layer to a semiconductor substrate. The trench is filled with a conductive material to electrically connect the body to the semiconductor substrate. Impurity ions are implanted into a predetermined region of the semiconductor substrate in contact with the lower portion of the body contact to form an ohmic contact. In the SOI MOSFET, an additional metal interconnection line is not needed to supply power to the body. Also, malfunction of a circuit due to stray capacitance of a contact can be prevented.
Abstract translation: 提供了具有用于防止浮体效应的身体接触的SOI MOSFET。 身体接触是将半体衬底穿孔的沟槽和掩埋氧化物层。 沟槽填充有导电材料以将本体电连接到半导体衬底。 将杂质离子注入到与身体接触的下部接触的半导体衬底的预定区域中以形成欧姆接触。 在SOI MOSFET中，不需要额外的金属互连线来为电源供电。 此外，可以防止由于接触的杂散电容引起的电路故障。
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公开(公告)号：US06539072B1
公开(公告)日：2003-03-25
申请号：US09524402
申请日：2000-03-13
Applicant: Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
Inventor： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC: H04L700
CPC classification number: H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.
Abstract translation: 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。
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公开(公告)号：US6163178A
公开(公告)日：2000-12-19
申请号：US222590
申请日：1998-12-28
Applicant: Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
Inventor： Donald C. Stark , Jun Kim , Kurt T. Knorpp , Michael Tak-Kei Ching , Natsuki Kushiyama
IPC: G11C7/10 , H03B1/00 , H03K17/16 , H03K19/003
CPC classification number: H03K17/164 , G11C7/1051 , H03K19/00384
Abstract: An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is controlled such that the output impedance of the output current driver is maintained within a predetermined range.
Abstract translation: 输出驱动器具有输出多路复用器和输出电流驱动器。 输出多路复用器接收数据信号并输出q-节点信号。 输出电流驱动器接收q-节点信号并根据q-节点信号驱动总线。 输出多路复用器以各种方式处理数据信号以产生q-结点信号。 输出电流驱动器响应于当前控制位以选择输出驱动电流的量。 此外，控制输出多路复用器，使得输出电流驱动器的输出阻抗保持在预定范围内。
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公开(公告)号：US6125157A
公开(公告)日：2000-09-26
申请号：US795657
申请日：1997-02-06
Applicant: Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
Inventor： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark
CPC classification number: H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0037 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H04L7/0008 , H04L7/0025
Abstract: Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.
Abstract translation: 延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。
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公开(公告)号：US5945862A
公开(公告)日：1999-08-31
申请号：US904203
申请日：1997-07-31
Applicant: Kevin S. Donnelly , Jun Kim , Bruno W. Garlepp , Mark A. Horowitz , Thomas H. Lee , Pak Shing Chau , Jared L. Zerbe , Clemenz L. Portmann , Yiu-Fai Chan
Inventor： Kevin S. Donnelly , Jun Kim , Bruno W. Garlepp , Mark A. Horowitz , Thomas H. Lee , Pak Shing Chau , Jared L. Zerbe , Clemenz L. Portmann , Yiu-Fai Chan
CPC classification number: H03K5/1565 , H03K5/13
Abstract: Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the incoming signal or at least half the period in the case of dual chains receiving complementary clocks. Phase adjustment circuitry includes a delay chain of having a plurality of taps, a boundary detector for indicating when a tap is at a phase boundary of the incoming periodic signal, and selection circuitry for selecting one of the taps from the delay chain based on the boundary detector output and the selection circuitry input such that the selected tap is the desired phase adjustment of the incoming periodic signal and that the delay of the incoming signal is adjustable across its phase boundaries. Phase interpolation between the taps of the delay chain is employed to increase the resolution of the adjustment to the periodic signal. Duty cycle correction of the input clock and the selected output clock is employed to improve accuracy.
Abstract translation: 用于在整个周期信号的整个周期内调整进入周期信号（通常为时钟信号）的相位的电路。 相位调整电路具有高分辨率，并且仅在延迟链中仅使用延伸元件的数量来跨越至少输入信号的周期，或者在双链接收互补时钟的情况下至少半个周期。 相位调整电路包括具有多个抽头的延迟链，边界检测器，用于指示抽头何时处于输入周期性信号的相位边界;以及选择电路，用于基于边界从延迟链中选择一个抽头 检测器输出和选择电路输入，使得所选择的抽头是输入周期性信号的期望的相位调整，并且输入信号的延迟在其相位边界上是可调节的。 使用延迟链的抽头之间的相位插值来增加对周期性信号的调整的分辨率。 采用输入时钟和选择的输出时钟的占空比校正来提高精度。
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