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107 条记录 (耗时 0.029 秒)

    NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE
    81.
    发明申请
    NONVOLATILE MEMORY DEVICE PROVIDING NEGATIVE VOLTAGE 有权
    提供负电压的非易失性存储器件

    公开(公告)号：US20130010539A1

    公开(公告)日：2013-01-10

    申请号：US13463063

    申请日：2012-05-03

    申请人： Sang-Won Shim ,  Pan-Suk Kwak ,  Ki-Tae Park ,  Yoon-Hee Choi

    发明人： Sang-Won Shim ,  Pan-Suk Kwak ,  Ki-Tae Park ,  Yoon-Hee Choi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30

    摘要： Disclosed is a nonvolatile memory device which includes memory blocks, a pre-decoder, and a row decoder. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.

    摘要翻译： 公开了一种非易失性存储器件，其包括存储器块，预解码器和行解码器。 每个存储块具有多个存储单元。 预解码器包括多路复用器和负电平移位器。 复用器被配置为响应于地址信号产生复用信号。 每个负电平移位器被配置为通过将具有接地电压的多路复用信号转换成具有第一负电压的转换多路复用信号来生成与各个多路复用信号相对应的转换的复用信号。 行解码器被配置为响应于转换的复用信号来选择至少一个存储器块。

    METHOD OF MERGING BLOCKS IN A SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE TO PERFORM A METHOD OF MERGING BLOCKS
    83.
    发明申请
    METHOD OF MERGING BLOCKS IN A SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE TO PERFORM A METHOD OF MERGING BLOCKS 有权
    在半导体存储器件中合并块的方法和用于执行合并块的方法的半导体存储器件

    公开(公告)号：US20110296087A1

    公开(公告)日：2011-12-01

    申请号：US13114262

    申请日：2011-05-24

    申请人： Min-Seok Kim ,  Ki-Tae Park

    发明人： Min-Seok Kim ,  Ki-Tae Park

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7205

    摘要： In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method.

    摘要翻译： 在根据示例性实施例的半导体存储器件中的块的合并方法中，使用第一编程方法将多个数据写入一个或多个第一块。 在一个或多个第一块中选择需要合并的一个或多个合并目标块。 在一个或多个第一块和一个或多个第二块中选择用于块合并操作的合并执行块。 使用与第一编程方法不同的第二程序方法，将多个合并目标数据从合并目标块写入合并执行块。

    Nonvolatile memory device, program method thereof, and memory system including the same
    84.
    发明授权
    Nonvolatile memory device, program method thereof, and memory system including the same 有权
    非易失性存储器件，其程序方法和包括该非易失性存储器件的存储器系统

    公开(公告)号：US08004898B2

    公开(公告)日：2011-08-23

    申请号：US12320092

    申请日：2009-01-16

    申请人： Ki-Tae Park ,  Yeong-Taek Lee

    发明人： Ki-Tae Park ,  Yeong-Taek Lee

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10

    摘要： A nonvolatile memory device may include a memory cell array adapted to store tail-bit flag information indicating tail-bit memory cells, and a tail-bit controller adapted to calibrate a program start voltage of normal memory cells and a program start voltage of the tail-bit memory cells independently based upon the tail-bit flag information.

    摘要翻译： 非易失性存储器件可以包括适于存储指示尾部位存储器单元的尾部位标志信息的存储单元阵列，以及用于校准正常存储单元的程序启动电压和尾部程序启动电压的尾位控制器 - 位存储单元独立地基于尾位标志信息。

    Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same
    85.
    发明授权
    Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same 有权
    使用基于年龄的验证电压来提高数据可靠性的闪存器件和操作方法

    公开(公告)号：US07692970B2

    公开(公告)日：2010-04-06

    申请号：US11943887

    申请日：2007-11-21

    申请人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

    发明人： Ki-Tae Park ,  Yong-Seok Kim ,  Ki-Nam Kim ,  Yeong-Taek Lee

    IPC分类号： G11C11/34

    CPC分类号： G11C16/344 ,  G11C16/3454

    摘要： Disclosed is a method of verifying a programmed condition of a flash memory device, being comprised of: determining a level of an additional verifying voltage in response to the number of programming/erasing cycles of memory cells; conducting a verifying operation to programmed memory cells with an initial verifying voltage lower than the additional verifying voltage; and selectively conducting an additional verifying operation with the additional verifying voltage to the program-verified memory cells in response to the number of programming/erasing cycles.

    摘要翻译： 公开了一种验证闪速存储器件的编程状态的方法，其包括：响应于存储器单元的编程/擦除循环的数量确定额外的验证电压的电平; 对初始验证电压低于附加验证电压的程序存储单元执行验证操作; 以及响应于所述编程/擦除周期的数量，选择性地对所述经过程序验证的存储器单元执行附加验证电压的附加验证操作。

    Nonvolatile memory device and driving method thereof
    86.
    发明授权
    Nonvolatile memory device and driving method thereof 有权
    非易失性存储器件及其驱动方法

    公开(公告)号：US07675783B2

    公开(公告)日：2010-03-09

    申请号：US12035732

    申请日：2008-02-22

    申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

    发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454

    摘要： Provided are a nonvolatile memory device and a driving method thereof. In the method of driving a nonvolatile memory device, a structural shape and position of a memory cell to be driven is determined, and then the memory cell is driven with an optimized operating condition according to a distribution of the memory cell using a determination result.

    摘要翻译： 提供一种非易失性存储装置及其驱动方法。 在驱动非易失性存储器件的方法中，确定要驱动的存储单元的结构形状和位置，然后使用确定结果根据存储单元的分布以优化的操作条件驱动存储单元。

    METHODS OF RESTORING DATA IN FLASH MEMORY DEVICES AND RELATED FLASH MEMORY DEVICE MEMORY SYSTEMS
    88.
    发明申请
    METHODS OF RESTORING DATA IN FLASH MEMORY DEVICES AND RELATED FLASH MEMORY DEVICE MEMORY SYSTEMS 有权
    在闪速存储器件中恢复数据的方法和相关的闪存存储器件存储器系统

    公开(公告)号：US20080094914A1

    公开(公告)日：2008-04-24

    申请号：US11616411

    申请日：2006-12-27

    申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

    发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

    IPC分类号： G11C16/04

    CPC分类号： G11C16/349 ,  G11C16/3495

    摘要： Methods for setting a read voltage in a memory system which comprises a flash memory device and a memory controller for controlling the flash memory device, comprise sequentially varying a distribution read voltage to read page data from the flash memory device; constituting a distribution table having a data bit number and a distribution read voltage, the data bit number indicating an erase state among the page data respectively read from the flash memory device and the distribution read voltage corresponding to the read page data; detecting distribution read voltages corresponding to data bit numbers each indicating maximum points of possible cell states of a memory cell, based on the distribution table; and defining new read voltages based on the detected distribution read voltages.

    摘要翻译： 包括闪速存储器装置和用于控制闪速存储器件的存储器控​​制器的存储器系统中设置读取电压的方法包括顺序地改变分配读取电压以从闪速存储器装置读取页面数据; 构成具有数据位数和分布读电压的分布表，分别表示从闪存器件分别读取的页数据中的擦除状态的数据位数和与读页数据相对应的分布读电压; 基于分布表，检测对应于每个表示存储器单元的可能单元状态的最大点的数据位数的分布读取电压; 以及基于检测到的分布读取电压来定义新的读取电压。

    Semiconductor memory device including plurality of memory chips
    90.
    发明授权
    Semiconductor memory device including plurality of memory chips 有权
    半导体存储器件包括多个存储器芯片

    公开(公告)号：US09129663B2

    公开(公告)日：2015-09-08

    申请号：US14108417

    申请日：2013-12-17

    申请人： Ki-Tae Park

    发明人： Ki-Tae Park

    IPC分类号： G11C5/02 ,  G11C8/12 ,  G11C5/14 ,  G11C7/20

    CPC分类号： G11C8/12 ,  G11C5/02 ,  G11C5/025 ,  G11C5/143 ,  G11C7/20

    摘要： A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips

    摘要翻译： 半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。 各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个 设备芯片