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128 条记录 (耗时 0.035 秒)

    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same
    82.
    发明授权
    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same 有权
    包括三维布置的存储单元晶体管的存储器件及其操作方法

    公开(公告)号：US07701771B2

    公开(公告)日：2010-04-20

    申请号：US11882769

    申请日：2007-08-06

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    IPC分类号： G11C11/03

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

    摘要翻译： 存储器件可以包括L个半导体层，每个半导体层上的栅极结构，N个位线和/或每个半导体层上的公共源极线。 L个半导体层可以被堆叠，和/或L可以是大于1的整数.N个位线可以在栅极结构上并且跨过栅极结构，和/或N可以是大于1的整数。 公共源极线可以彼此连接，使得公共源极线彼此具有等电位。

    Phase change memory device and method for forming the same
    84.
    发明申请
    Phase change memory device and method for forming the same 失效
    相变存储器件及其形成方法

    公开(公告)号：US20080173862A1

    公开(公告)日：2008-07-24

    申请号：US12008125

    申请日：2008-01-09

    申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    IPC分类号： H01L45/00

    CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

    摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

    摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

    Ferroelectric memory devices having expanded plate lines
    85.
    发明授权
    Ferroelectric memory devices having expanded plate lines 有权
    具有扩展板线的铁电存储器件

    公开(公告)号：US07285810B2

    公开(公告)日：2007-10-23

    申请号：US10948610

    申请日：2004-09-23

    申请人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

    发明人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

    IPC分类号： H01L31/0224

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

    摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.

    摘要翻译： 铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，其被布置为在行和列方向上的多个行和列。 多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。 多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过 绝缘层中的开口。 在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。 相邻行中的铁电电容器可以共享公共铁电电介质区域。 讨论相关的制造方法。

    STACKED FERROELECTRIC MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, FERROELECTRIC MEMORY CIRCUITS AND METHODS OF DRIVING THE SAME
    86.
    发明申请
    STACKED FERROELECTRIC MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, FERROELECTRIC MEMORY CIRCUITS AND METHODS OF DRIVING THE SAME 失效
    堆叠式电磁存储器件，其制造方法，电磁存储器电路及其驱动方法

    公开(公告)号：US20070189056A1

    公开(公告)日：2007-08-16

    申请号：US11675007

    申请日：2007-02-14

    申请人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

    发明人： Heung-Jin Joo ,  Byung-Gil Jeon ,  Byoung-Jae Bae ,  Ki-Nam Kim

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22 ,  G11C11/221 ,  G11C11/223

    摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

    摘要翻译： 堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖 位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层 夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。 铁电存储器件执行随机存取操作并具有高集成度。

    Methods of fabricating ferroelectric memory devices having expanded plate lines
    87.
    发明授权
    Methods of fabricating ferroelectric memory devices having expanded plate lines 有权
    制造具有扩展板线的铁电存储器件的方法

    公开(公告)号：US07208367B2

    公开(公告)日：2007-04-24

    申请号：US11029232

    申请日：2005-01-04

    申请人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

    发明人： Hyun-Ho Kim ,  Dong-Jin Jung ,  Ki-Nam Kim ,  Sang-Don Nam ,  Kyu-Mann Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507

    摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.

    摘要翻译： 铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，其被布置为在行和列方向上的多个行和列。 多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。 多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过 绝缘层中的开口。 在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。 相邻行中的铁电电容器可以共享公共铁电电介质区域。 讨论相关的制造方法。

    Ferroelectric memory device and control method thereof
    89.
    发明授权
    Ferroelectric memory device and control method thereof 失效
    铁电存储器件及其控制方法

    公开(公告)号：US06967860B2

    公开(公告)日：2005-11-22

    申请号：US10683663

    申请日：2003-10-09

    申请人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

    发明人： Mun-Kyu Choi ,  Byung-Jun Min ,  Ki-Nam Kim ,  Byung-Gil Jeon

    IPC分类号： G11C11/22 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A ferroelectric random access memory device including a pulse generator circuit capable of generating a pulse signal in response to an address transition. A chip enable buffer circuit activates a chip enable flag signal in response to a first transition of the pulse signal. A row selector circuit selects and drives one of the rows in response to the address. The row selector circuit also generates a flag signal indicating a selection of a plate line. A control circuit activates a plate control signal in response to the activation of a write enable signal, and deactivates the plate control signal in response to a second transition of the pulse signal. A plate line of a selected row is re-activated according to activation of the plate control signal and is deactivated according to deactivation of the plate control signal.

    摘要翻译： 一种铁电随机存取存储器件，包括能够响应于地址转换产生脉冲信号的脉冲发生器电路。 芯片使能缓冲电路响应于脉冲信号的第一转换而激活芯片使能标志信号。 行选择器电路响应于地址选择并驱动其中一行。 行选择器电路还产生指示板线选择的标志信号。 响应于写入使能信号的激活，控制电路激活板控制信号，并且响应于脉冲信号的第二转换而使板控制信号无效。 根据板控制信号的激活，所选行的板线被重新激活，并且根据板控制信号的去激活而被去激活。

    Semiconductor memory device and method for manufacturing the same
    90.
    发明授权
    Semiconductor memory device and method for manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US06949429B2

    公开(公告)日：2005-09-27

    申请号：US10796098

    申请日：2004-03-10

    申请人： Ki-Nam Kim ,  Byung-Jun Park

    发明人： Ki-Nam Kim ,  Byung-Jun Park

    IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/60 ,  H01L21/8242

    CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/55 ,  H01L28/91

    摘要： A semiconductor memory device and a method for manufacturing the same are provided. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate, a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area, a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistor, a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area is interposed, a guard-ring pattern, which are interposed between the cell area and the peripheral circuit area, surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern. The guard-ring pattern is formed in a boundary between the cell area and the peripheral circuit area while surrounding the cell area, and thereby step caused by manufacture of the stack-shaped capacitor are removed during a manufacturing process, and the contact fill for plate electrode is formed in the guard-ring pattern, and thereby the ground resistance of the capacitor is reduced, and the electrical characteristics of the memory device are improved.

    摘要翻译： 提供半导体存储器件及其制造方法。 半导体存储器件包括用于隔离各个器件的氧化物层，其限定器件区域，使得在半导体衬底上的单元区域和外围电路区域彼此分离，由源极区域构成的多个MOS晶体管，漏极 形成在单元区域和外围电路区域中的区域和栅极，形成在多个MOS晶体管上并与MOS晶体管电连接的位线，堆叠形状的电容器，其由 第一电极，电介质层和第二电极，MOS晶体管和单元区域中的位线之间插入有保护环图案，其被插入在单元区域和外围电路区域之间，围绕单元区域 并且与外围电路区域分离，并且用于平板电极的接触填充物，其形成为保护环图案并与形成的第二电极接触 在内侧壁和保护环图案的底部。 保护环图案形成在单元区域和外围电路区域之间的边界周围，同时围绕单元区域，并且由此在制造过程中移除由堆叠形电容器的制造引起的步骤，并且板的接触填充 电极形成为保护环图案，从而降低了电容器的接地电阻，并提高了存储器件的电气特性。