公开(公告)号：US5680175A

公开(公告)日：1997-10-21

申请号：US513022

申请日：1995-08-09

申请人： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

发明人： Norifumi Yanai ,  Ryo Fujita ,  Koyo Katsura ,  Yasushi Fukunaga

IPC分类号： G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/399 ,  H04N5/262 ,  H04N7/26 ,  H04N7/50 ,  H04N7/01

CPC分类号： G09G5/39 ,  G06T1/20 ,  H04N19/42 ,  H04N19/61 ,  H04N5/2624 ,  G09G2340/125 ,  G09G2360/123 ,  G09G5/36 ,  G09G5/399

摘要： An image composing and displaying apparatus includes frame memory constituent elements of an identical structure, a video input portion, a video output portion, a controller for selecting connection of each element to the video input or output portion, and an image drawing portion for reading and writing video data from and in the memory elements. The memory elements can be used for the input and output operations and hence the size thereof can be easily expanded; moreover, the numbers of the elements respectively connected to the video input and output portions can be adaptively varied.

摘要翻译： 图像合成显示装置包括具有相同结构的帧存储器组成元件，视频输入部分，视频输出部分，用于选择每个元素与视频输入或输出部分的连接的控制器，以及用于读取和/ 从存储器元件中写入视频数据。 存储元件可用于输入和输出操作，因此其尺寸可以容易地扩展; 此外，分别连接到视频输入和输出部分的元件的数量可以自适应地变化。

公开(公告)号：US5657045A

公开(公告)日：1997-08-12

申请号：US430851

申请日：1995-04-28

申请人： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

发明人： Koyo Katsura ,  Hideo Maejima ,  Hisashi Kajiwara

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T11/20 ,  G06T17/00 ,  G09G5/02 ,  G09G5/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G5/38

CPC分类号： G09G5/395 ,  G06T1/20 ,  G06T1/60 ,  G06T11/203 ,  G06T17/00 ,  G09G5/024 ,  G09G5/20 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G09G2360/127 ,  G09G5/36

摘要： A graphic data generating apparatus includes a data processor, a graphic memory, and a graphic processor. The data processor outputs instructions to the graphic processor for processing graphic data. The instructions include a drawing instruction for transferring graphic data stored in a predetermined location in the graphic memory to another predetermined location in the graphic memory. The graphic memory stores pixel data defining the graphic data and each of the pixel data having a plurality of bits. The graphic processor performing read out of word data having a plurality of pixel data at a word position of the graphic memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the graphic memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.

摘要翻译： 图形数据生成装置包括数据处理器，图形存储器和图形处理器。 数据处理器向图形处理器输出指令以处理图形数据。 指令包括用于将存储在图形存储器中的预定位置的图形数据传送到图形存储器中的另一预定位置的绘图指令。 图形存储器存储定义图形数据的像素数据，并且每个像素数据具有多个位。 图形处理器执行读出由源存储器地址指定的图形存储器的字位置处的多个像素数据的字数据，选择由读出字中的源像素地址指定的像素数据，并将所选择的像素数据写入 在由目的地存储器地址指定的字数据的目标像素地址指定的像素位置处的图形存储器。

公开(公告)号：US5373469A

公开(公告)日：1994-12-13

申请号：US890260

申请日：1992-05-29

申请人： Takashi Akioka ,  Noboru Akiyama ,  Yutaka Kobayashi ,  Tatsuyuki Ohta ,  Koyo Katsura

发明人： Takashi Akioka ,  Noboru Akiyama ,  Yutaka Kobayashi ,  Tatsuyuki Ohta ,  Koyo Katsura

IPC分类号： G11C11/417 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  G11C11/414 ,  H03K19/013 ,  H03K19/0944 ,  G11C7/00 ,  H03K19/086

CPC分类号： H03K19/09448 ,  G09G5/363 ,  G09G5/393 ,  G11C7/062 ,  G11C7/065 ,  H03K19/0136 ,  G09G2360/121

摘要： A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.

摘要翻译： 公开了一种采用流水线技术的高速存储器，其中通过使用双极晶体管的小信号的锁存电路来减小最小工作周期时间。 操作在小于输出信号电平的信号的小信号锁存电路被插入放大器电路，用于放大存储单元电路中保存的数据和输出缓冲电路。 开关信号也插入在锁存电路和放大器电路之间，从而缩短了周期时间。

公开(公告)号：US4677549A

公开(公告)日：1987-06-30

申请号：US469047

申请日：1983-02-23

申请人： Koyo Katsura ,  Hideo Maejima

发明人： Koyo Katsura ,  Hideo Maejima

IPC分类号： G06F9/38 ,  G06F9/22 ,  G06F9/28 ,  G06F13/00

CPC分类号： G06F9/3824 ,  G06F9/28

摘要： The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.

摘要翻译： 本发明涉及一种基于流水线控制系统的数字数据处理器，当读取微程序所需的时间相对较短时，该处理器特别有效。 微循环基于读取微程序所需的时间，并且通过根据确定的微循环将其分割在管道系统中来执行对数据的操作。 这通过在算术单元的输出侧提供目的地锁存寄存器来完成。 本发明还涉及其中目的地锁存寄存器被提供在运算单元的输入侧上，或者当目的地锁存寄存器被并入运算单元内的处理器，以及用于避免任何可能对寄存器进行争用的电路设置 在执行当前指令时产生，并且根据添加的微程序提供下一指令。

公开(公告)号：USRE39529E1

公开(公告)日：2007-03-27

申请号：US09536646

申请日：2000-03-28

申请人： Koyo Katsura ,  Shinichi Kojima ,  Noriyuki Kurakami

发明人： Koyo Katsura ,  Shinichi Kojima ,  Noriyuki Kurakami

IPC分类号： G09G5/39

CPC分类号： G09G5/393

摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.

摘要翻译： 存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器 提供并行数据处理。 在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。 结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

公开(公告)号：US06751605B2

公开(公告)日：2004-06-15

申请号：US09789820

申请日：2001-02-22

申请人： Keiko Gunji ,  Koyo Katsura ,  Soshiro Kuzunuki ,  Masaki Miura ,  Toshimi Yokota

发明人： Keiko Gunji ,  Koyo Katsura ,  Soshiro Kuzunuki ,  Masaki Miura ,  Toshimi Yokota

IPC分类号： G06F1730

CPC分类号： G06K9/72 ,  G06K2209/01 ,  Y10S707/99931 ,  Y10S707/99933

摘要： A character recognition apparatus for inferring the entire character string solely from a user-input handwritten keyword and displaying the inferred result as a candidate character string. The apparatus of the invention comprises: a word string includes a word hierarchy and for recognizing each of the words within the hierarchy; a character transition probability table a4 storing probabilities of transitions from any one character to another, and those pieces of the word identification information which correspond to combinations of characters resulting from the transitions; and an optimization unit for using the character transition probability table in optimizing candidate character strings obtained by a recognition unit. The word dictionary is searched for a word defined by the word identification information which corresponds to the optimized candidate character string, whereby the searched word is retrieved which applies to the hierarchy information and which has yet to be input.

摘要翻译： 一种字符识别装置，用于仅从用户输入的手写关键词中推断出整个字符串，并将推测的结果显示为候选字符串。本发明的装置包括：字串包括字层级，并用于识别每个字 在层次结构中 存储从任何一个字符到另一个字符的转换概率的字符转换概率表a4，以及对应于由转换产生的字符的组合的那些字识别信息; 以及优化单元，用于在通过识别单元获得的优化候选字符串中使用字符转换概率表。 搜索单词词典由对应于优化的候选字符串的单词识别信息定义的单词，由此检索适用于层级信息并且尚未被输入的搜索词。

公开(公告)号：US06677950B1

公开(公告)日：2004-01-13

申请号：US08996151

申请日：1997-12-22

申请人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

发明人： Mamoru Ohba ,  Mitsuru Watabe ,  Rika Minami ,  Koyo Katsura

IPC分类号： G06T1500

CPC分类号： G06T11/203

摘要： To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and 2 multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes 2 line drawing procedure that uses data tables and 2 multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data. Thus, the graphics computer hardware is reduced in size and the cost of the hardware is reduced.

摘要翻译： 为了减小图形计算机的硬件尺寸并降低硬件成本，将帧缓冲器和主存储器联合成一个单元来处理CPU中的图形数据。 帧缓冲器布置在主存储器中，并且图形计算机包括用于从帧缓冲器读取像素数据以进行显示的DMAC，用于接收像素数据并将其显示在诸如LCD的显示设备上的显示器， 以及用于存储CPU使用的程序来绘制所述帧缓冲器中的像素数据的存储器。 特别地，所述存储器被形成为使得可以选择单个功能过程和2多功能过程以适合绘图对象。 另外，单功能过程包括使用数据表的2行绘图过程和使用模式表和掩码表的2多值扩展过程。 由于帧缓冲器和主存储器被组合成一个单元，所以CPU可以用于处理图形数据。 因此，图形计算机硬件的尺寸减小，硬件的成本降低。

公开(公告)号：US06377267B1

公开(公告)日：2002-04-23

申请号：US09593496

申请日：2000-06-14

申请人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

发明人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

IPC分类号： G06F1300

CPC分类号： G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/127

摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。

公开(公告)号：US06288728B1

公开(公告)日：2001-09-11

申请号：US09583721

申请日：2000-05-30

申请人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

发明人： Jun Satoh ,  Kazushige Yamagishi ,  Keisuke Nakashima ,  Koyo Katsura ,  Takashi Miyamoto ,  Mitsuru Watabe ,  Kenichiroh Ohmura

IPC分类号： G06F1576

CPC分类号： G09G5/393 ,  G06F1/04 ,  G06F1/12 ,  G06F12/0207 ,  G06F13/1689 ,  G06F13/4243 ,  G06F15/7832 ,  G06T1/60 ,  G09G5/001 ,  G09G5/395 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2350/00 ,  G09G2360/128 ,  G09G2370/10 ,  G11C8/04 ,  G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18

摘要： A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

摘要翻译： 一种数据处理器，包括：总线控制电路，适于与可与时钟信号同步地访问的同步DRAM接口; 耦合到所述总线控制电路的多个数据处理模块，用于产生访问存储器的数据和地址; 以及时钟驱动器，用于将本征操作时钟馈送到所述数据处理模块，并且用于馈送用于与所述操作时钟信号操作的所述数据处理模块的操作同步地访问所述存储器的时钟信号。

公开(公告)号：US06222563B1

公开(公告)日：2001-04-24

申请号：US09327355

申请日：1999-06-08

申请人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

发明人： Koyo Katsura ,  Yasushi Fukunaga ,  Ryo Fujita ,  Kazuyoshi Koga ,  Takehiko Nishida

IPC分类号： G06F15167

CPC分类号： G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/127

摘要： A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

摘要翻译： 一种用于生成，显示或打印字符和图形数据的图形处理装置。 使用连续的列访问，其中指定行地址用于访问存储器，并且连续地访问指定的相同行地址内的不同列地址中的数据，以及缓冲装置，用于在处理器的访问和 提供对内存的访问。 用于显示的程序和图像信息存储在主存储器中。 帧缓冲器和主存储器的整体结构简单，体积小。