公开(公告)号：US10726917B1

公开(公告)日：2020-07-28

申请号：US16254962

申请日：2019-01-23

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/04 ,  G11C7/10 ,  G11C16/28

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

公开(公告)号：US20200234761A1

公开(公告)日：2020-07-23

申请号：US16254962

申请日：2019-01-23

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/04 ,  G11C16/28 ,  G11C7/10

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

公开(公告)号：US10692557B1

公开(公告)日：2020-06-23

申请号：US16381702

申请日：2019-04-11

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

公开(公告)号：US10475498B2

公开(公告)日：2019-11-12

申请号：US15653276

申请日：2017-07-18

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/404 ,  G11C11/409 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4091 ,  G11C5/14 ,  G11C7/06 ,  G11C27/02

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.

公开(公告)号：US10475489B2

公开(公告)日：2019-11-12

申请号：US16020834

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/14 ,  G11C11/22 ,  G11C11/24 ,  G11C11/408 ,  G11C5/06 ,  G11C8/08 ,  G11C8/14 ,  G11C5/14

Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

公开(公告)号：US10446502B2

公开(公告)日：2019-10-15

申请号：US15691055

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Daniele Vimercati

IPC: H01L23/552 ,  H01L23/528 ,  H01L27/108 ,  H01L27/11507 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/409 ,  G11C11/16 ,  G11C11/408 ,  G11C11/4094 ,  G11C13/00 ,  G11C7/10 ,  G11C7/08

Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.

公开(公告)号：US10416909B2

公开(公告)日：2019-09-17

申请号：US16253087

申请日：2019-01-21

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Claudio Resta ,  Marco Ferraro

IPC: G06F3/06 ,  H01L45/00 ,  G11C13/00 ,  G11C13/02

Abstract: Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.

公开(公告)号：US20190252407A1

公开(公告)日：2019-08-15

申请号：US16391479

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: H01L27/11597 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/1159 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11587

CPC classification number: H01L27/11597 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/1159 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/7827 ,  H01L29/78391

Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

公开(公告)号：US10304513B2

公开(公告)日：2019-05-28

申请号：US16041455

申请日：2018-07-20

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C13/00 ,  G11C11/22 ,  H01L27/11502 ,  H01L27/11514 ,  H01L27/11507

Abstract: Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.

公开(公告)号：US20180358090A1

公开(公告)日：2018-12-13

申请号：US16045523

申请日：2018-07-25

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Ferdinando Bedeschi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2213/72

Abstract: A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.