中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

139 records (took 0.025 seconds)

    Apparatuses, systems, and methods for managing metadata security and access
    81.
    发明授权
    Apparatuses, systems, and methods for managing metadata security and access 有权

    公开(公告)号：US12204770B2

    公开(公告)日：2025-01-21

    申请号：US17730992

    申请日：2022-04-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi

    IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16

    Abstract: Apparatuses, systems, and methods for managing access to metadata stored at a memory. To manage access to metadata, a mode register is configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting. A metadata access control circuit configured to receive a column address identifying a particular column to be accessed within a memory array. The metadata access control circuit blocks access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, and permits access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.

    FAST BACKGROUND ARRAY PATTERN WRITING
    82.
    发明申请
    FAST BACKGROUND ARRAY PATTERN WRITING 有权

    公开(公告)号：US20240404574A1

    公开(公告)日：2024-12-05

    申请号：US18678630

    申请日：2024-05-30

    Applicant: Micron Technology, Inc.

    Inventor： Sujeet Ayyapureddi

    IPC: G11C11/00 ,  G11C11/4072 ,  G11C11/4078 ,  G11C16/20 ,  G11C16/22

    Abstract: To ensure proper functioning of a memory component, the memory cells may be initialized to a known value before the memory device is used. The known values are termed the “background pattern.” The memory cells may also be reset to the background pattern to scrub data memory for security. Typically, standard write operations are used to write the background pattern. As discussed herein, multiple addresses on a single word line can be written to simultaneously. As also discussed herein, when the same data is written to multiple word lines, the step of copying the data to the sense amplifiers may be performed once instead of repeated for each write command, further reducing the time consumed by writing background patterns to a memory array.

    APPARATUSES AND METHODS FOR READ COMMANDS WITH DIFFERENT LEVELS OF ECC CAPABILITY
    84.
    发明公开
    APPARATUSES AND METHODS FOR READ COMMANDS WITH DIFFERENT LEVELS OF ECC CAPABILITY 审中-公开

    公开(公告)号：US20240296095A1

    公开(公告)日：2024-09-05

    申请号：US18588402

    申请日：2024-02-27

    Applicant: Micron Technology, Inc.

    Inventor： Sujeet Ayyapureddi

    IPC: G06F11/10

    CPC classification number: G06F11/1076

    Abstract: Apparatuses, systems, and methods for read commands with different levels of error correction code (ECC) capability. A memory receives a first type of read command and reads data with a first level of ECC and receives a second type of read command and reads the data with a second level of ECC. For example, single error correction (SEC) may be used as part of the first type of read command and more errors may be detected/corrected as part of the second type of read command. A controller may read data using the first type of read command and if a signal is received indicating that an error was detected may read the data again using the second type of read command.

    APPARATUSES, SYSTEMS, AND METHODS FOR PER ROW ERROR SCRUB INFORMATION
    86.
    发明公开
    APPARATUSES, SYSTEMS, AND METHODS FOR PER ROW ERROR SCRUB INFORMATION 审中-公开

    公开(公告)号：US20240248796A1

    公开(公告)日：2024-07-25

    申请号：US18625539

    申请日：2024-04-03

    Applicant: Micron Technology, Inc.

    Inventor： Sujeet Ayyapureddi

    IPC: G06F11/10

    CPC classification number: G06F11/106

    Abstract: Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

    Apparatuses, systems, and methods for managing metadata storage at a memory
    87.
    发明授权
    Apparatuses, systems, and methods for managing metadata storage at a memory 有权

    公开(公告)号：US12014797B2

    公开(公告)日：2024-06-18

    申请号：US17731024

    申请日：2022-04-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sujeet Ayyapureddi

    IPC: G11C7/10 ,  G06F12/06

    CPC classification number: G11C7/1039 ,  G06F12/06 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/1096

    Abstract: Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during an metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.

    APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF
    88.
    发明公开
    APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF 审中-公开

    公开(公告)号：US20240160524A1

    公开(公告)日：2024-05-16

    申请号：US18504342

    申请日：2023-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

    IPC: G06F11/10

    CPC classification number: G06F11/1044

    Abstract: Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Patent Agency Ranking